68HC11%20Timer

1
68HC11 Timer

• Chapter 10

2
68HC11 Timer Subsystem

• Several timing functions
• Basic timing
• Real time interrupts
• Output compare
• Input capture
• Computer Operating Properly
• Pulse Accumulator
• Pulse Width Modulation
• Common Features
• Based on a central timer
• Overflow Flags
• Interrupt Enables

3
Timer System Block Diagram
4
Basic Timer
5
Basic Timer TCNT100E

• 16-bit free running counter (timer)
• Cannot be set or stopped.
• Fclk system clock
• Can be prescaled by 1,4,8, or 16
• Read only at memory address (100E)
• Overflow flag is bit 7 in TFLG2 (1025)
• Can use overflow to extend counters range
• Timer Overflow Interrupt Enable
• Bit 7 in TMSK (1024)

6
TCNT - 100E100FTimer Counter Register
CNT13
CNT12
CNT11
CNT10
CNT9
CNT8
100E
CNT14
CNT15
100F
CNT5
CNT4
CNT3
CNT2
CNT1
CNT0
CNT6
CNT7
Bits
READ ONLY Register
7
Prescaler
Timer Interrupt Mask Register 2 1024 --
TFLG2
PR1
PAII
0
0
PAOVI
RTH
TOI
PR2
Bits
PR1,PR0 Timer prescale select - Timer Clock
System Clock / Prescale Factor
Pr1 Pr0 Prescale Factor 0 0
1 0 1
2 1 0 4 1
1 16
8
Timer Overflow Flag
Miscellaneous Timer Interrupt Flag Register 2
1025 (TFLG2)
0
PAIF
0
0
PAOVF
RTIF
TOF
0
Bits
TOF Timer overflow flag -
0 No overflow
1 Overflow TOF is reset to 0 by
writing 1 to TOF
9
Timer Overflow Interrupts
Timer Interrupt Mask Register 2 1024
(TMSK2)
PR1
PAII
0
0
PAOVI
RTH
TOI
PR2
Bits
TOI Timer overflow interrupt enable
0 disable interrupt
1 enable interrupt
10
Basic Timer Example

• Problem Write an ISR to read the input from
  PortC and write it to PortB approximately every
  1,000,000 clock cycles. Assume timer prescale
  1

11
Basic Timer ExampleMain Program

• Configure Timer Overflow Interrupt
• TMSK2(7) ? 1
• Enable Interrupts (CLI)
• Repeat
• Until Forever
• Set Timer Overflow Interrupt Vector
• ORG TOI_VECTOR (FFDEFFDF)
• FDB TO_ISR

12
Basic Timer ExampleTO_ISR

• Disable Interrupts
• SEI
• Turn-off Interrupt Request
• TOF ? 1
• CNT CNT 1
• IF CNT MAX_CNT then
• CNT 0
• A ? PORTC
• PORTB ? A
• END IF
• Return from Interrupt

13
Basic Timer ExampleMAX_CNT Calculation

• Need to wait 1,000,000 or F4240 clock cycles.
• Interrupt is generated every 65536 or 10000
  clock cycles
• Max_CNT INT(1,000,000 / 65556) 15.258 15
  F
• Note INT(F4240/10000) F
• Set MAX_CNT EQU F

14
Real Time Interrupt
15
Real Time Interrupt

• Similar to Timer Overflow Interrupt except
• We have
• RTI Flag (RTIF) Bit 6 in TFLG2 (1025)
• RTI Enable (RTII) Bit 6 in TMSK2 (1024)
• System Clock is first divided by 1000 then
  divided again by the prescale bits given by RTR1
  and RTR0 in PACTL (1026)

16
Real Time Interrupt Enable
Timer Interrupt Mask Register 2 1024
(TMSK2)
PR1
PAII
0
0
PAOVI
RTII
TOI
PR2
Bits
RTII Real Time Interrupt Enable
0 disable interrupt
1 enable interrupt
17
Real Time Interrupt Flag
Miscellaneous Timer Interrupt Flag Register 2
1025 (TFLG2)
0
PAIF
0
0
PAOVF
RTIF
TOF
0
Bits
RTIF Real Time Interrupt flag -
1 RTI has
occurred RTIF is reset to 0 by writing 1 to
RTIF
18
Real Time InterruptPrescale
Port A Control Register 1026 (PACTL)
RTR1, RTR0 Real Time Interrupt Prescale
RTR1 RTR0 Nominal RTI rate (2MHz
E-Clock) 0 0
4.096ms 0 1
8.192ms 1 0
16.384ms 1 1
32.768ms
19
TPS Quiz
20
Computer Operating Properly

• COP

21
Computer Operating ProperlyCOP

• Also known as a watchdog timer
• When enabled, your program must set the COP timer
  and reset the COP timer prior to the COPs
  time-out delay. This time-out delay is
  programmable.
• If the program does not set or reset the COP
  timer before the time-out, a COP failure
  interrupt is generated and the ISR assigned to
  the interrupt is executed.

22
Computer Operating ProperlyCOP

• Usage
• Design your program to set and reset the COP
  before time-out.
• If your program enters an infinite loop, the COP
  timer will time-out automatically causing a COP
  failure interrupt.
• Use the COP failure ISR to place your system into
  a safe mode or restart mode.

23
Output Compare
24
Timer Output Compare

• Using the timer overflow flag or interrupt will
  generate a count every 65536 clock cycles.
• Given a 2MHz clock, this gives a sample
  resolution of 32.8ms
• The timer output compare feature allows for more
  precise timing.

25
Timer Output Compare

• There are five output compare registers
• Each with a separate
• Compare Counter
• Interrupt Mask
• Overflow Flag

26
TOC1 TOC5 Timer Output Compare Registers
OCn13
OCn12
OCn11
OCn10
OCn9
OCn8
OCn14
OCn15
OCn5
OCn4
OCn3
OCn2
OCn1
OCn0
OCn6
OCn7
Bits
TOC1 - 10161017 TOC2 - 10181019 TOC3 -
101A101B
TOC4 - 101C101D TOC5 - 101E101F
27
Output Compare Flags
Main Timer Interrupt Flag Register 1 1023
(TFGL1 )
IC2F
OC4F
IC1F
OC5F
OC3F
OC2F
OC1F
IC3F
Bits
OC1F-OC5F Output Compare Flags 1
when output compare register equals TCNT
0 reset by writing 1 to bit position
28
Output Compare Interrupts
Main Timer Interrupt Mask Register 1 1022
(TMSK1)
IC2I
OC4I
IC1I
OC5I
OC3I
OC2I
OC1I
IC3I
Bits
OC1I-OC5I Output Compare interrupt enable
0 disable interrupt
1 enable interrupt
29
Output Compare Example

• Problem Write an ISR to read the input from
  PortC and write it to PortB approximately every
  10,000 clock cycles. Assume timer prescale 1
• Note 10,000 cycles is less than one timer
  overflow!!

30
Output Compare ExampleMain Program

• A? TCNT Load current count
• TOC1 ? A 10000 Add 10000 to current count
• Configure Output Compare 1 Interrupt
• TMSK1(7) ? 1
• Enable Interrupts (CLI)
• Repeat
• Until Forever
• Set Output Compare 1 Interrupt Vector
• ORG OC1_VECTOR (FFE8FFE9)
• FDB OC1_ISR

31
Output Compare ExampleOC1_ISR

• Disable Interrupts
• SEI
• Turn-off Interrupt Request
• OC1F ? 1
• A ? PORTC
• PORTB ? A
• A ? TCNT Load current count
• TOC1 ? A10000 update TOC1 for next
• interrupt
• Return from Interrupt

32
Input Capture
33
Timer Input Capture
TCNT
16-bit TCIx Latch
Ext Signal
Det Ckt
PAx
clk
When the Ext Signal is detected on pin PAx, the
current value of the free running counte TCNT is
latched into the timer input capture latch. This
value can be read and saved to determine the time
between events.
34
Timer Input Capture

• The timer input capture feature can be used to
  time external events
• Three input capture registers
• TIC1 10101011
• TIC2 10121013
• TIC3 10141015
• Maximum time between events must be less than
  65536 cycles

35
TIC1 TIC3 Timer Input Capture Registers
ICn13
ICn12
ICn11
ICn10
ICn9
ICn8
ICn14
ICn15
ICn5
ICn4
ICn3
ICn2
ICn1
ICn0
ICn6
ICn7
Bits
TIC1 - 10101011 TIC2 - 10121013 TIC3 -
10141015
36
Input Compare Interrupts
Main Timer Interrupt Mask Register 1 1022
(TMSK1)
IC2I
OC4I
IC1I
OC5I
OC3I
OC2I
OC1I
IC3I
Bits
IC1I-IC3I Input Compare interrupt enable
0 disable interrupt
1 enable interrupt
37
Interrupt Capture Flags
Main Timer Interrupt Flag Register 1 1023
(TFGL1 )
IC2F
OC4F
IC1F
OC5F
OC3F
OC2F
OC1F
IC3F
Bits
IC1F-IC3F Interrupt Capture Flags 1
when selcted edge is detected 0
reset by writing 1 to bit position
38
Timer Control Register 2TCTL2 - 1021
EDG1B
EDG1A
EDG2B
EDG2A
EDG3B
EDG3A
0
0
Bits
EDGnB EDGnA Configuration 0
0 Disabled 0
1 Rising Edge 1
0 Falling Edge
1 1 Either
Edge
39
Pulse Accumulator
40
Pulse Accumulator

• The pulse accumulator can be used as an event
  counter. That is, it can count the number of
  external events.
• Note difference to Timer Input Capture which
  counts the time between external events.
• Configuration
• PACTL (1026) is used to configure PA
• PACNT (1027) is the PA Count Register
• Two Modes
• Event Counting PA7 is External Clock
• Gated Time Accumulation PA7 is enable to system
  clock divided by 64

41
PACTL 1026Port A Control Register
PAEN6 Pulse Accumulator System Enable 0
Disable (Default) Port A is set for I/O
function 1 Enable Port A is set for
Pulse Accumulator function
PAMOD Pulse accumulator mode 0 Event counter
(Default) 1 Gated time accumulation
42
PACTL 1026Port A Control Register
PEDGE Pulse Accumulator Edge Select 0
Falling Edge (in event mode) Active High (in
gated mode) 1 Rising Edge (in event mode)
Active Low (in gated mode)
43
Pulse Accumulator Flag
Miscellaneous Timer Interrupt Flag Register 2
1025 (TFLG2)
0
PAIF
0
0
PAOVF
RTIF
TOF
0
Bits
PAOVF Pulse Accumulator Overflow Flag
1
Overflow has occurred PAOVF is reset to 0 by
writing 1 to PAOVF
PAIF Pulse Accumulator Input Edge Flag
1 Input
edge has been detected PAIF is reset to 0 by
writing 1 to PAIF
44
Pulse Accumulator Interrupts
Timer Interrupt Mask Register 2 1024
(TMSK2)
PR1
PAII
0
0
PAOVI
RTII
TOI
PR2
Bits
PAOVI Pulse Accumulator overflow interrupt
enable 0 disable
interrupt 1 enable
interrupt
PAII Pulse Accumulator input edge interrupt
enable 0 disable
interrupt 1 enable
interrupt
45
Pulse Width Modulation
46
Pulse Width Modulation

• Some versions of 68HC11 have a pulse width
  modulation (PWM) module which can be used to
  generate periodic output waveforms with a
  specific period and duty cycle (i.e. the
  percentage of time the signal is high compare to
  when it is low).

47
Timer Summary

• Timer subsystem most complex in 68HC11
• Based on free running timer
• Timings available
• Basic timing
• Real time interrupts
• Output compare
• Input capture
• Computer Operating Properly
• Pulse Accumulator
• Pulse Width Modulation
• Overflow flags and/or Interrupts are available