Chap' 5: Control Design - PowerPoint PPT Presentation

Loading...

PPT – Chap' 5: Control Design PowerPoint presentation | free to download - id: 1a7dc2-ZDc1Z



Loading


The Adobe Flash plugin is needed to view this content

Get the plugin now

View by Category
About This Presentation
Title:

Chap' 5: Control Design

Description:

Used in early CPU designs (before about 1960) Also used in RISC CPU ... Instruction re-ordering (like Fig. 5.57c) Can be done by compiler or CPU H/W logic ... – PowerPoint PPT presentation

Number of Views:99
Avg rating:3.0/5.0
Slides: 33
Provided by: sungg
Learn more at: http://www.postech.ac.kr
Category:

less

Write a Comment
User Comments (0)
Transcript and Presenter's Notes

Title: Chap' 5: Control Design


1
Chap. 5 Control Design
  • CPU Control Logic Design Methods
  • Hardwired Control
  • Used in early CPU designs (before about 1960)
  • Also used in RISC CPU designs (1985 current)
  • Necessary for high performance
  • Typically uses PLAs for the combinational logic
  • Microprogrammed Control
  • Used in CISC CPU designs
  • Suitable for highly complex control unit designs

2
Hardwired Control
  • Finite State Machine Method
  • Suitable only for small designs
  • Compact state diagrams and state transition
    tables can be used ? Fig. 5.11 (p. 317)
  • Algorithmic State Machine Method
  • Similar to using compact state diagrams
  • Systematic method suitable for large designs
  • One-hot or PLD-based control logic design

3
  • Several examples shown in textbook
  • Fig. 5.1 and 5.2 (pp. 304-305)
  • Example of CPU design DP ? control signals ?
    CU (Data ? status signals ?
    (ControlProcessing Unit) Unit)
  • GCD (Greatest Common Divisor) Processor
  • Special-purpose processor
  • Block diagram of design shown in Fig. 5.6 (p.
    311)
  • DMA Controller (pp. 315-319)
  • Multiplier Control (pp. 319-325)
  • Simple Accumulator-based CPU (pp. 326-331)

4
Hardwired Control Using EPROMs
Other PLD types can also be used
Lee 2000
5
Microprogrammed Control
  • Originally proposed by M. V. Wilkes in 1951
  • Systematic control logic design method in which
    control signals are generated using a low-level
    program (a microprogram) stored in a fast on-chip
    ROM (referred to as control memory (CM))
  • Widely used from about 1960 early 1980s
  • Useful for designing control logic for
    microprocessors with extremely large and complex
    instruction sets

6
Lee 2000
7
Microinstruction Formats
  • Vertical Format
  • Sets of control signals are encoded into control
    fields
  • Decoders are used to generate the actual control
    signals from a specific microinstruction
  • Horizontal Format
  • Control signals are generated directly form the
    microinstruction (no encoding or decoding is used)

Refer to Fig. 5.31 (p. 338)
8
Lee 2000
9
Lee 2000
10
Lee 2000
11
Extensions
  • Each microinstruction can be executed in several
    clock phases ? Fig. 5.32 (p. 339)
  • Leads to nanoprogramming ? Fig. 5.51(362)
  • Each microinstruction is executed by a series of
    naninstructions stored in a nanoprogram memory
  • Actually used in Motorolla 68020 to reduce CM
    size
  • Bit-sliced microproprogrammed sequencers can be
    used ? Fig. 5.35

12
Pipeline Control
  • Possible Methods
  • Use microprogramming and pipeline the
    microprogram control unit ? Fig. 5.54
  • Encode the pipelined control into the
    microprogram ? refer to pp. 149-150
  • Generate all necessary control signals at the
    first stage and then pipeline the control signals
  • Replicate registers and other modules as necessary

13
Example
  • Design a 16-bit microcomputer with 16 regs. (R0,
    , R15), PC, and instruction set
  • MOV Ry, Rx Ry ? Rx
  • ADD Ry, Rx Ry ? Ry Rx
  • AND Ry, Rx Ry ? Ry and Rx
  • Use microprogrammed control
  • Assume simple 2-stage instruction pipeline

14
Datapath Design
  • ASM Chart and Datapath slight modification of
    Figs. 6.10 and 6.11 (221-222) of Lee 2000s0.
    IR ? MPC PC 2c0. If (IR MOV Ry, Rx)
    goto s1 else if (IR ADD Ry, Rx) goto
    s2 else if (IR AND Ry, Rx) goto
    s3s1. Ry ? Rx IR ? MPC PC 2 goto
    c0s2. Ry ? Ry Rx IR ? MPC PC 2
    goto c0s3. Ry ? Ry Rx IR ? MPC PC 2
    goto c0

15
Instruction Format Design
  • Design a simple format which makes the datapath
    and control logic design easierbit position15
    14 13 12 11 10 9 8 7 6 5 4 3 2 1
    0 opcode Ry Rx
  • If (IRlt70gt 0101 1011) then Ry R5 and Rx
    R11
  • Use opcode 0000 0001 for MOV Ry, Rx, opcode
    0000 0010 for ADD Ry, Rx, ...

16
Possible Datapath Design
17
Control Logic Design
LoadYReg, RegYSel, RegXSel, ALUFunSel
Lee 2000
18
Contents of the Control Memory (CM)
19
Instruction Pipeline Example
  • MIPS R2000/R3000 Pipeline (Ex. 5.7)
  • five-stage pipeline (IF, RD, EX, MA, WB)
  • Fig. 5.56 (p. 368) maximum utilization
  • Fig. 5.57 (p. 369) pipeline delays (stalls)
  • Instruction Pipeline Performance Measure
  • CPI (Clock) Cycles Per Instruction
  • Equation 5.22
  • CPI f / MIPS, where f clock frequency

20
Main Memory
Instruction Cache
Data Cache
IF
Instruction Fetch (IR MPC PC 2)
RD
Read Registers (ALUy Ry ALUx Rx)
EX
Execute (ALUout ALUy operation ALUx)
MA
Memory Access (for LOAD or STORE)
WB
Write Back (Rz ALUout)
21
An Example of a Sequence of Simple to Pipeline
Instructions
  • Instruction I1 MOVE R1, R0 I2 ADD R4,
    R3, R2 I3 SUB R6, R5, R3 I4 OR R7,
    R2, R0
  • No data dependencies or branches (jumps)
  • Results in space-time diagram of Fig. 5.56
  • What is the CPI for the above set of instr.?

22
An Instruction Sequence with Pipeline Hazards
  • Instruction I1 LOAD R1, addr1 I2 ADD R3,
    R2, R1 I3 JUMPC location2 location2 I4
    SUB R5, R4, R3
  • data hazard
  • control hazard (due to jump)
  • Leads to space-time diagram like Fig. 5.57a

23
Methods for Dealing with Pipeline Hazards
  • Instruction re-ordering (like Fig. 5.57c)
  • Can be done by compiler or CPU H/W logic
  • Branch prediction
  • A while or for loop will typically result in
    a jump back to the beginning of the loop
  • Data forwarding
  • Use ALUout of the previous instruction as an
    input to the ALU for the current instruction

24
Advanced Pipelining Techniques
  • Superscalar Processing
  • Use several copies of some H/W resources
  • Execute 2-5 instructions concurrently
  • Refer to Fig. 5.66 (p. 385)
  • Superpipeline Processing
  • Use a large number of stages (about 10-20)
  • Efficiency is similar to Fig. 5.66c. Why?
  • VLIW (use extremely wide instr. words)

25
Control of Pipelines with Complex Structures
(nonlinear, dynamic, )
  • In general, a difficult problem
  • For special case of a sequence of instructions
    that use the pipeline in the same manner
  • Use a pipeline reservation table
  • Example shown in Fig. 5.62 (p. 376)
  • More general examples shown in Lee 2000

26
Dynamic Nonlinear Pipeline Example
Pipeline Structure
Pipeline Reservation Table
27
Problem and Solution Approach
Problem When should the next instruction be
executed?
Solution Approach Use a pipeline reservation
table to determine when conflicts for
pipeline resources can occur.
28
Systematic Solution Approach
  • Given instruction I, form the pipeline
    reservation table R
  • Form the forbidden list of of R
  • Form the initial collision vector CV0
  • Form the task initiation diagram (TID)
  • Find a cycle with the minimum average latency in
    the TID
  • Corresponds to optimal initiation schedule

29
Example 10.7 of Lee 2000
Find the optimal pipeline initiation schedule for
an instruction J, which has the pipeline
reservation table shown.
30
Steps 2 and 3
  • Step 2 Form the forbidden list
  • set of all time intervals that can result in
    collisions
  • row 1 1, 4, 5 row 2 1 row 3 none
    row 4 none
  • thus, forbidden list (1, 4, 5)
  • Step 3 Form the initial collision vector
  • bit vector representation of the forbidden list
  • CV0 c1c2c3c4c5 10011
  • Step 4 Form the task initiation diagram (TID)
  • consider all possible subsequent collision
    vectors

31
Step 4 Form TID -gt start new state
for every 0 bit position
Step 5 Find a schedule with minimum average
latency -gt look at all possible
cycles and calculate average
latencies as (sum of labels / number of arrows)
32
Resulting Optimal Pipeline Initiation Schedule
for Instr. J
Question What is the steady-state pipeline
utilization?
About PowerShow.com