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Telecom Access Application

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External SDRAM interface for up to 256MB of frame storage memory. ... are stored in SDRAM before transit. IXF3502. x3 ... 32 MB PC100-compliant SDRAM per device ... – PowerPoint PPT presentation

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Title: Telecom Access Application


1
Telecom Access Application
  • September 2002
  • YS Kim
  • Field Application Engineer

2
DS3 Channelized Line Cards
3
OC-3 Channelized Line Card
4
OC-12 Channelized Line Card
5
Product Details
  • IXF3501/3 Mapper/Framer
  • IXF3502 HDLC Controller

6
IXF35013 T3/STS-3 OHT-MAPPER-FRAMER
To IXF3502
7
IXF3501
  • Available today
  • Proven solution
  • SONET/T1 only but easy migration pass to
    SONET/SDH
  • IXF3503 is HW and SW compatible
  • Designed to be used with IXF3502 HDLC
  • Works for multiple line cards
  • 3 or 6 T3
  • Single, Dual or Quad OC3
  • Single, or Dual OC12

8
IXF3501 Features
  • Flexible channelization from STS-3 level down to
    64 Kbps
  • Four devices can be combined to process a full
    STS-12 payload without external multiplexer or
    overhead terminator.
  • Processes SONET overhead in STS-3 and STS-12
    modes
  • Serial ports for overhead access and Automatic
    Protection Switching (APS)
  • Optional Interface to three DS3 LIUs working as a
    triple M13 multiplexer with integrated DS3 and
    DS1 framers
  • Features integrated VT1.5 mappers, DS3 mappers,
    M13 multiplexers and integrated DS1 and DS3
    framers
  • Serial DS3 interfaces on terminal side for
    payload access and manipulation in fractional DS3
    implementations

9
IXF3501 Features (cont.)
  • DS1 framers can operate in ESF, D4, or
    transparent modes. Provisionable on a per channel
    basis
  • Offers optional slip buffering in both transmit
    and receive directions
  • Supports ESF data-link Bit-Oriented Messages
    (BOM) and HDLC-based PRM messages
  • Pin efficient Octet Stream Interface (OSIF)
    connects seamlessly to IXF3502 HDLC controller
  • Optional H-MVIP/H.100 compatible TDM interface
    running at 8.192 MHz
  • Programmable Remote Test Unit (RTU) for
    pseudo-random test pattern insertion and
    detection
  • 32-bit PCI bus operating at 33 MHz for
    configuration, control and status

10
IXF35033 T3/OC3 SONET/SDH Mapper/Framer
To IXF3502
11
IXF35033T3/STS-3 STM-1 SONET/SDH Mapper/Framer
  • In design
  • Variation of IXF3501
  • Pin to Pin compatible
  • Software compatible
  • Works for multiple line cards
  • 3 or 6 T3
  • Single, Dual or Quad OC3 SONET/SDH STS-3/STM-1
  • Single or Dual OC12
  • Sampling Q302
  • Production Q402

12
IXF3503 Features
  • Flexible channelization from STS-3/STM-1 level
    down to 64 Kbps
  • Four IXF3503 devices can be combined to process a
    full STS-12/STM-1 payload without external
    multiplexer or overhead terminator.
  • Processes SONET/SDH overhead in STS-3/STM-1 and
    STS-12/STM-4 modes
  • Serial ports for overhead access and Automatic
    Protection Switching (APS)
  • Optional Interface to three DS3 LIUs working as a
    triple M13 multiplexer with integrated DS3 and
    DS1 framers
  • Features integrated VT1.5/TU-11/TU-12 mappers,
    DS3/E3 mappers, M13 multiplexers and integrated
    DS1/E1 and DS3/E3 framers
  • Serial DS3/E3 interfaces on terminal side for
    payload access and manipulation in fractional
    DS3/E3 implementations

13
IXF3503 Features (cont.)
  • DS1 framers support ESF, D4, or transparent
    modes. E1 framing per G.704 and CRC-4 modes.
    Provisionable on a per channel basis
  • Offers optional slip buffering in both transmit
    and receive directions
  • Supports ESF data-link Bit-Oriented Messages
    (BOM) and HDLC-based PRM messages
  • Pin efficient Octet Stream Interface (OSIF)
    connects seamlessly to IXF3502 HDLC controller
  • Optional H-MVIP/H.100 compatible TDM interface
    for easy connection to standard Time Slot
    Interchange (TSI) devices
  • Programmable Remote Test Unit (RTU) for
    pseudo-random test pattern insertion and
    detection
  • 32-bit PCI bus operating at 33 MHz for
    configuration, control and status

14
IXF3501/03 OC-12 Line Interface
SONET/SDH Ser/Des CK Recovery
TXODAT70
TXOSYNC
TXPCLK
TXOCLK
RXOOF
030 (Master)
RXPDAT70
DATA07
RXSYNC
RXICLK
TXIDAT70
CK
SYNC
TXODAT70
TXISYNC
TXICLK
03
1 (
Slave)
RXPDAT70
RXSYNC
TXIDAT70
RXICLK
TXODAT70
TXISYNC
TXICLK
03
2 (
Slave)
RXPDAT70
RXSYNC
TXIDAT70
RXICLK
TXISYNC
TXODAT70
TXICLK
03
3 (
Slave)
RXPDAT70
RXSYNC
RXICLK
15
IXF35021024 channel HDLC
From IXF3501 or IXF3503
16
IXF3502
  • Available today
  • Proven solution
  • Can handle up to 1024 channels
  • Range Subrate DS0, DS0, DS1, Fractional DS3,
    DS3, E1, E3
  • Frame bandwidth 4x DS3 or 179Mb/s
  • Store and Forward technology
  • Integrates segmentation, reassembly and buffering
  • No need for external complex circuitry
  • Much easier implementation and frame management
  • Reduces framer loss risks

17
IXF3502 Features
  • Supports up to 1024 bidirectional HDLC channels.
  • Flexible channelization support from sub-rate DS0
    up to a full DS3 payload.
  • OSIF Interface connects seamlessly to the Intel
    IXF3501/3
  • Selectable flag delineation/insertion, bit
    stuffing/de-stuffing and optional checksum
    calculation/verification per CRC-16 or CRC-32.
  • External SDRAM interface for up to 256MB of frame
    storage memory.
  • Built-in context storage memory.
  • Extensive HDLC performance monitoring and
    statistics including per channel CRC errored
    frames, non-octet aligned frames and good bytes
    count.
  • High-speed POS-PHY Level 2 switch interface.
  • 32-bit PCI bus operating at 33 MHz for
    configuration, control and status monitoring.

18
IXF3502 Frame Store Then Forward Architecture
System side begins here
Frames are stored in SDRAM before transit
Line side
SDRAM
Buffering
Complete Frames Bursted on POS-PHY
Multi Channel HDLC Octets
x3
HDLC
Assembly
eof
sof
eof.sof
STS-12 application
HDLC
Segmentation
sofeof
sof
eof
IXF3502
19
Cut-through HLDC Architecture
System side begins here
Completed Frames Bursted on POS-PHY
Multi Channel Frame segments
Line side
Multi Channel HDLC Octets
External Memory
HDLC
Assembly
eof.sof
eof
sof
STS-12 application
Buffering
HDLC
sof.eof
Segmentation
sof
eof
Total of 1-4 support devices required
20
Evaluation BoardsandSoftware
21
IXF3501 Evaluation Board
  • Supports both OC-3 and OC-12 modes
  • Supports DS3 electrical Interface through LIUs
  • Controlled by external MBX860 Microprocessor
    Board
  • R-232 interface for control and status (menu
    based)
  • Reference schematics and layout documentation
  • Connects directly to the IXF3502 evaluation board

22
IXF3502 Evaluation Board
  • Supports up to OC-12 aggregate bandwidth
  • 32 MB PC100-compliant SDRAM per device
  • Controlled by external MBX860 Microprocessor
    Board (shared with 3501)
  • R-232 interface for control and status (menu
    based)
  • Reference schematics and layout documentation
  • Connects directly to the IXF3501 evaluation board

23
IXF3501/02 Evaluation Boards
3501 Evaluation Board
3502 Evaluation Board
3501
3502
3501
3502
FR/PPP Packets
C O N N.
C O N N.
C O N N.
3501
OSIF or H.100
SONET OC-3 orOC-12
SERDES
3501 (master)
3502
PCI bus
C O N N.
C O N N.
3 xDS3
CONN.
Host PC
ISI Development. Kit
JAVA application
MPC860 bus
PCI bus
Windows
R T O S
QSPAN
MPC860
SCC1
SMC1
MBX860 Board
24
Software Support
  • Menu based interface for eveluation board control
    and configuration
  • All drivers and software are written in standard
    C language
  • Source code running under pSOS or VxWorks Real
    Time Operating System
  • Software drivers do not contain RTOS specific
    commands for improved portability
  • Software includes different tools for
    initialization, diagnostics, monitoring and
    interrupt processing

25
ROADMAP
  • IXF3504 and IXF3505

26
Roadmap
Available
In definition
In design
2nd Generation
1st Generation
Morganville 2 IXF3502 OC3 1024 HDLC
Manteo IXF3505 OC12 2048 HDLC-MLPPP
Morganville 1 IXF3501 3T3/OC3 SONET Mapper/Framer
Pamlico IXF3504 OC12 Mapper/Framer
Swansboro IXF3503 OC3 SONET/SDH Mapper/Framer
Orion LXT3108 8 T1/E1 LIU
SOL IXF3208 8 T1/E1 Framer
MIAMI 16 T1/E1 LIU
2H01
1H02
1H01
2H02
1H03
2H03
1H04
2H04
27
IXF3504 OC12 SONET/SDH Mapper/Framer
To IXF3505
28
IXF3504OC12 SONET/SDH Mapper/Framer
  • Reusing IXF3503 core
  • In definition stage
  • On chip Performance Report Messages and
    Monitoring
  • Optional Fractional DS3 support
  • Works for multiple line cards
  • 12 T3/E3
  • Single, Dual or Quad OC12
  • Single OC48

29
IXF35052048 channel HDLC-MLPPP Controller
To IXF3504
30
IXF35052048 channel HDLC-MLPPP Controller
  • Capable of handling 4 times the bandwidth of
    IXF3502
  • Up to 2048 channels
  • Supports MLPPP
  • 168 ML-PPP bundles
  • 12 channels per bundles
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