Algorithms and tools for Computer Aided Circuit Design

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Algorithms and tools for Computer Aided Circuit
Design

• Seminar on
• Direct RTL to Layout Conversion
• By
• Soundarrajan Vaitheeswaran
• Infotech
• Institut für Technische Informatik

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Overview

• Introduction
• Traditional Approach and its drawbacks
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Introduction

• Why this new approach ?

• Advancements in semiconductor technology

• Increase in design complexity

• Shorter time-to-market

• Need for effective and efficient synthesis -
  higher abstraction

• High level synthesis decisions crucial

• Significant variation in hardware attributes

• specific technology

• physical design

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A typical sequential top-down VLSI chip design
process
Behavioral Description
Constraint Met ?
High Level Synthesis
Physical Design
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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Drawbacks of Traditional Approach

• Explore a large number of solutions

• Verification of constraints tedious and
  time-consuming

• Run place and route for every candidate solution

• If constraints not met, difficult to identify
  the level in design flow

• HLS and physical design considered separate

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Drawbacks of Traditional Approach

• Wire delay ignored

• Unpredictable placement and routing

• Unpredictability more pronounced when started
  from behavioral level

• Several iterations for an acceptable solution

• Offset turnaround time of FPGA

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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Layout driven approach with ChipEst
Behavioral Description
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Layout Driven Synthesis

• Features

• Accurate, efficient prediction of design metrics
  - reduces run time

• Incorporates layout information in design
  process

• ChipEst-FPGA - chip level efficient area and
  performance estimator

• CompEst-FPGA - component level estimation tool -
  predicts area and
• delay of a RTL component netlist.

• Optimum final layout without time-consuming
  place and route

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Layout Driven Synthesis

• Features

• Resolves the confusion over constrains
  violation

• Component area, timing and wiring taken into
  account

• Hierarchical Compiler for High Level Synthesis

• Synopses Floorplan compiler (2002)
• http//www.synopsys.com/products/floorplan_compile
  r/floorplan_compiler.html

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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Problem Definition

• Given
• Behavioral Description
• A number of Funtional units
• Registers
• Multiplexers
• Maximum clock period

• Assess the chip topology, cost and performance

• Identify feasible RTL solution

• If there is, generate a RTL netlist and floorplan

• Else, report to previous task and output best
  possible solution

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Problem Solution

• How does it work ?

• Initial fully connected netlist

• CompEst-FPGA

• predicts the shape function of RTL components

• estimates the area and delay of
  non-precharacterized components

• ChipEst-FPGA

• generates approximate topology of the chip

• predicts the approximate device it may fit

• Binding algorithm generates RTL netlist

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Layout Driven Binding
Behavioral Description
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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Chip Area Estimation

• CompEst tool gives actual delay information

• Shape function of entire design S shape
  functions of individual blocks

• Best possible solution

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Chip Area Estimation

• Cutting edge threshold - tradeoff between area
  and performance

• Similar sized object adjacent to each other

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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Chip Level Wiring Delay Estimation

• Component - pinlocation

• Wire segment delay

• Programmable Interconnect Point (PIP) delay

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Chip Level Wiring Delay Estimation

• Calculate Manhatten distance along x and y axes
  (in CLBs)

• Assign wire type based on interconnect wire
  length

• PIP and number of segments between any two
  points known

• Compute Data path delay

• Determine Clock cycle time worst case
  register-to-register delay

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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Layout Driven Binding
c
Behavioral Description
Binding Success?
c
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Layout Driven Binding

• Binding performed sequentially one control
  step at a time

• Virtual binding - FU and storage binding
  output variables - input
• variables

• Cut-off point for Binding paths with delay
  greater than this not used

• Initial cut-off point worst case
  register-to-register delay

• Once cut-off point set solution conforming to
  the constraints is found

• Better solutions explored by lowering the
  cut-off point

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Layout Driven Binding

• Compatibility Check

• if enough paths with delay less than cut-off
  point to perform binding

• If operator can be assigned to the FU, variables
  to registers

• Resource Check

• If available resources are sufficient to perform
  binding

• Feasibility check performed for every virtual
  bound

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Layout Driven Binding - Algorithm
Procedure Binding (Si, N, M, allocation
resource) Inputs Si the ith source
objects (1 i N where N is the number of
source objects) Tij the jth target
objects (1 j M where M is the number of
target objects) / objects FU, Ovar,
Ivar / Output Binding solution begin
Procedure for ( j 1 to M) if
(FeasibilityCheck(Si, Tij, allocation resource))
then VirtualBinding(Si, Tij) if
(i 1 N) then success
Binding(Si1, N, M) if (success)
then return (True)
else UnBindVirtualBinding(Si ,
Tij) end if else
ActualBinding return (True)
end if end if end for
return(False) end Procedure
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Layout Driven Binding
c
Behavioral Description
Binding Success?
YES
Pruning
NO
c
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Layout Driven Binding

• Pruning

• All unnecessary interconnects are pruned

• Unwanted multiplexors are deleted

• Area and Timing information updated in the
  library

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Layout Driven Binding

• Layout Adjustment

• If clock period exceeds the constraint

• ChipEst rerun on pruned RTL netlist

• Minimizes wasted area, improves performance

• If constraints not met

• Binding with a new cut-off point

• Till cut-off point reaches threshold

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Layout Driven Binding
Layout adjustment
Component design Est.
c
Pruned netlist
Binding Success?
NO
Library
YES
Best RTL feasible
NO
Constraint Met ?
YES
RTL netlist
c
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Layout Driven Binding
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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Experimental Results

• Discrete cousine transformer

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Experimental Results

• Layout and interconnect delays upto 50

• 6 average estimation error of performance

• Atleast twice faster than traditional layout
  process

• Each solution took less than a minute of CPU time

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Where are we ?

• Introduction
• Drawbacks of Traditional Approach
• Layout Driven Synthesis
• Problem Definition and Solution
• Chip Area Estimation
• Chip Wiring Delay Estimation
• Layout Driven RTL Binding
• Experimental Results
• Summary and Future Work

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Summary and Future Work

• Summary

• Layout information included in the design flow

• Faster output owing to prior knowledge of Chip
  topology

• Search space explored minimized

Disadvantage

• Include design information for all possible
  layout types

• Future Work

• Including layout information in the step of
  Allocation and Scheduling

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