A New Twisted Differential Line Structure in Global Bus Design

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A New Twisted Differential Line Structure in
Global Bus Design

• Zhanyuan Jiang, Shiyan Hu and Weiping Shi
• ECE Department
• Texas AM University

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1. Introduction

• The effect of crosstalk noise is increasingly
  important due to VLSI scaling.
• Capacitive noise
• Inductive noise
• Conventional single-end based noisereduction
  technique is not sufficient toreduce inductive
  noise.
• Power/ground shielding
• Increasing metal to metal separation
• Buffer insertion

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Single-end Bus Model

• Each signal line is sandwiched by a power trace
  and a ground trace.
• Middle line serves as the observation point for
  the noise.

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Differential Signaling

• Differential signaling effectively reduces both
  capacitive and inductive noise.
• 95.7 noise reduction can be obtained by this
  technique compared with power/ground shielding.
  Massoud, et al. DAC 2001
• Differential signaling fails to handle asymmetric
  noise sources.
• Twisted differential line (TDL) is proposed to
  balance the amount of noise at each trace. Zhong,
  et all. ICCAD 2000

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Twisted Differential Line

• In TDL, two parallel traces are used to transmit
  the complementary signals and the two traces are
  twisted periodically.

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Noise Signal

• Input frequency is 6GHz.
• Noise Margin0.15V, 10 of input signal voltage.
• Peak noise
• Single-end Model0.35V
• TDL0.11V.
• Ideal TDL provides reliable signal transmission.

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Challenge and Solution

• Challenge
• The performance of fabricated TDL is much worse
  than simulated performance.
• Finding and Solution
• It is suspected that the via resistance variation
  is the cause and our simulations confirm this.
• Redundant via insertion to reduce via resistance
  variation and avoid signal distortion.
• Buffer insertion to synchronize the transmitted
  signals.

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2. Non-ideal TDL-Via insertion
Output Signal without via resistance variation
Output Signal with via resistance variation
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Via Resistance Variation

• Sources of output signal distortion
• Via Resistance variation
• Interconnect height variation
• Supply voltage variation.
• Gate oxide thickness variation

Dominant factor!
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Single Via Layout
Complete symmetric, more space.
Not complete symmetric, less space.
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Redundant Via Layout
Complete symmetric, more space.
Not complete symmetric, less space.
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Noise Signal

• Peak noise
• Single via0.11V
• Double vias0.07V
• Triple vias0.04V

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Peak Noise vs. Resistance
The peak noise decreases with resistance and
increases with resistance difference. It is more
sensitive to resistance difference.
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3.Synchronization-buffer insertion

• Output signal is greatly out of synchronization.
  The maximum output difference (sync-error) is
  37ps.

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Problem Formulation

• Given a bus topology and a buffer library, find a
  buffer assignment such that the sync-error at the
  receiver of the bus is minimized subject to
  spacing constraint on buffers.
• Spacing Constraint Buffers can not be placed
  overlapped.

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Spacing Constraint
Candidate buffer positions
A feasible solution.
Violation!
An infeasible solution.
Violation!
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Algorithm

• The algorithm is dynamic programming and only
  returns the solutions satisfying spacing
  constraints.
• Solution tuple (Q, C)
• Q required arrival time
• C total downstream
  capacitance

At the driver, minimum sync-error solution is
returned.
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Improvement

• The sync-error decreases to 7ps compared with
  original 37ps.

before buffer insertion
after buffer insertion
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4. Conclusion

• Techniques proposed
• Redundant via insertion to reduce via resistance
  variation and avoid signal distortion
• Buffer insertion to provide signal
  synchronization
• Result
• A 6GHz signal can be transmitted reliably in TDL,
  without distortion and with synchronization.