14:332:331 Computer Architecture and Assembly Language Fall 2006 Week 11: Microprogramming

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14332331Computer Architecture and Assembly
LanguageFall 2006Week 11 Microprogramming

• Adapted from Dave Pattersons UCB CS152 slides
  and
• Mary Jane Irwins PSU CSE331 slides

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Simplifying Control Design

• For an implementation of the full MIPS ISA
• instructions can take from 1 clock cycle to 20
  clock cycles
• resulting in finite state machines with hundreds
  to thousands of states with even more arcs (state
  sequences)
• Graphical representations become impossibly
  complex
• Instead, represent the set of control signals
  that are asserted during a state as a low-level
  control instruction to be executed by the
  datapath
• microinstructions
• Executing the microinstruction is equivalent to
  asserting the control signals specified by the
  microinstruction

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Microprogramming

• Microinstruction has to specify
• what control signals should be asserted
• what microinstruction should be executed next
• Each microinstruction corresponds to one state in
  the FSM and is assigned a state number (or
  address)
• Sequential behavior increment the state
  (address) of the current microinstruction to get
  to the state (address) of the next
• Jump to the microinstruction that begins
  execution of the next MIPS instruction (state 0)
• Branch to a microinstruction based on control
  unit input using dispatch tables
• need one for microinstructions following state 1
• need another for microinstructions following
  state 2
• The set of microinstructions that define a MPS
  assembly language instruction (macroinstruction)
  is its microroutine

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Defining a Microinstruction Format

• Format the fields of the microinstruction and
  the control signals that are affected by each
  field
• control signals specified by a field usually have
  functions that are related
• format is chosen to simplify the representation
  and to make it difficult to write inconsistent
  microinstructions
• i.e., that allow a given control signal be set to
  two different values
• Make each field of the microinstruction
  responsible for specifying a nonoverlapping set
  of control signals
• signals that are never asserted simultaneously
  may share the same field
• seven fields for our simple machine
• ALU control SRC1 SRC2 Register control
  Memory PCWrite control Sequencing

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Review Multicycle Data and Control Path
PCWriteCond
PCWrite
PCSource
ALUOp
IorD
Control FSM
MemRead
ALUSrcB
MemWrite
ALUSrcA
MemtoReg
RegWrite
IRWrite
RegDst
PC31-28
Instr31-26
Shift left 2
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Instr25-0
2
0
1
Address
Memory
0
PC
Read Addr 1
0
A
Read Data 1
IR
Register File
1
zero
1
Read Addr 2
Read Data (Instr. or Data)
0
ALUout
ALU
Write Addr
Read Data 2
Write Data
1
B
0
Write Data
1
4
1
0
2
Sign Extend
Shift left 2
3
Instr15-0
ALU control
32
Instr5-0
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Review Multicycle RTL Summary
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Our Microinstruction Format
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Our Microinstruction Format, cont
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Dispatch (Branch) Logic

• Dispatch operations are implemented using special
  logic (PLAs)

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Creating the Microprogram

• Fetch microinstruction

• Label field represents the state (address) of the
  microinstruction
• Fetch microinstruction assigned state (address) 0

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Creating the Microprogram, cont

• Decode microinstruction

• Decode microinstruction assigned state (address) 1

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Creating the Microprogram, cont

• Decode microinstruction

• Decode microinstruction assigned state (address) 1

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Creating the Microprogram, cont

• Memory-reference (lw sw) microinstructions

• Assigned states (addresses) 2, 3, 4, and 5

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Creating the Microprogram, cont

• Memory-reference (lw sw) microinstructions

• Assigned states (addresses) 2, 3, 4, and 5

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Creating the Microprogram, cont

• R-type instruction microinstructions

• Assigned states (addresses) 6 and 7

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Creating the Microprogram, cont

• R-type instruction microinstructions

• Assigned states (addresses) 6 and 7

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Creating the Microprogram, cont

• Branch (beq) and jump microinstructions

• Assigned states (addresses) 8 and 9

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Creating the Microprogram, cont

• Branch (beq) and jump microinstructions

• Assigned states (addresses) 8 and 9

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The Entire Control Microprogram
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Microprogram to Microcode

• A microassember is used to convert the mnemonic
  microprogram into the actual control signals (0s
  and 1) or microcode, for example

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Microcode Implementation
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
Control PLA
Outputs
PCSource
ALUOp
ALUSourceB
ALUSourceA
RegWrite
RegDst
AddrCtl
1
Microprogram Counter
Adder
System clock
Addr select logic
sequencing control
Op0
Op1
Op2
Op3
Op4
Op5
Inst31-26
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Address Select Logic
to control PLA
1
System Clock
Microprogram Counter
Adder
2
1
0
3
0
Dispatch PLA_2
Dispatch PLA_1
Addr select logic
Op0
Op1
Op2
Op3
Op4
Op5
Inst31-26
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Review FSM Implementation
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
MemtoReg
Combinational control logic
PCSource
Outputs
ALUOp
ALUSourceB
ALUSourceA
RegWrite
RegDst
Inputs
Op0
Op1
Op2
Op3
Op4
Op5
Next State
State Reg
Inst31-26
System Clock
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Control Path Design Alternatives
Finite state diagram
Initial representation
Microprogram
Microprogram counter dispatch PLAs
Sequencing control
Explicit next state function
Logic representation
Logic equations
Microcode
Implementation technique
Programmable Logic Array (PLA)

• Microprogram representation advantages
• Easier to design, write, and debug