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Simulation in the process of system design Application to trafficlights monitoring and control Contr

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Title: Simulation in the process of system design Application to trafficlights monitoring and control Contr


1
Simulation in the process of system
designApplication to traffic-lights monitoring
and controlContribution to task 3.1
  • Ramón Martínez, Miguel Calvo, Leandro de Haro
  • ramon_at_gr.ssr.upm.es
  • Universidad Politécnica de Madrid
  • SPAIN

2
Scope
  • Impact of simulation in the process of system
    design
  • Methodology to go from specifications to
    implementation following a simulation approach
  • Physical layer simulation
  • and even layer 0 (hardware)
  • Simulation tasks in the process of developing a
    prototype
  • Application to modems for traffic light
    monitoring and control
  • using powerlines as the communication channel
  • Simulation tools (commercial)
  • How different tools interact and work
    together
  • Validation and verification (from simulation to
    measurement)

3
Development cycle
Tasks
1) Design and specification
2) Implementation
3) Verification and validation
4
Motivation
  • Problems detected with incandescent lamps
  • Power consumption
  • Reduced lifetime
  • Misleading operation
  • Low flexibility

5
Scope
  • Specify a smart system with distributed
    intelligence for traffic-light control
    (implemented with LEDs)
  • Design and implement low cost modems
  • Validate the prototype by simulation and
    measurements

6
Specifications
  • Traffic lights based on LEDs
  • New methods for the detection of burned out lamps
  • Low cost infraestructure for the communication
    system
  • PLC through LV power lines
  • Distributed intelligence in the network
  • Reduced complexity for the central regulator
  • Refresh period 100 msec
  • For road safety reasons
  • Monitoring of upto 32 status
  • The proposed solution must be flexible
  • Traffic light groups of 8 lights maximum
  • The proposed solution must be modular

7
Task 1
  • Prior to implementation
  • selection of communication system
  • Modulation, multiple acess, bit rate
  • Take into account signal specifications and
    channel condition
  • Results physical layer parameters
  • Simulation tool Matlab

8
System architecture

Regulator
9
Multiplexing
time
Time slot
10
Multiplexing
11
Frame format
  • Echonet specification

12
Physical layer parameters
  • Carrier frecuency 400 KHz
  • Base band sampling frequency 2 MHz
  • Oversampling frequency in D/A 100 MHz
  • Chip rate (code) 400 kchip/s
  • Bit rate 12.5 kbit/s
  • Digital modulation BPSK (SF32)

13
Task 2
  • Implementation
  • Division of the system in modules (filtering,
    modulation)
  • Integration of modules
  • Hardware code of individual modules (hardware
    compiler) ISE
  • Harware description languaje VHDL (Very High
    Speed Integrated Circuit Hardware Description
    Language )
  • Compilation is ok
  • Hardware simulation of individual modules
    ModelSim
  • Timing is correct
  • Simulation of hardware with real signals
  • Matlab for generation of actual (noisy) signals
  • Interface with Matlab Link for ModelSim

14
Hardware code in VHDL (ISE)
15
Transmitter
LV network (channel)
CLOCKGEN
DUC
Regulator
GENERA_SLOT
16
Hardware verification (ModelSim)
17
Task 3
  • Once the prototype is finished
  • validation and verification through
    measurements
  • In case printed circuit boards are required
    (i.e., filtering, interface with powerline
    channel, etc.) MultiSim

18
FPGA board
  • Xilinx FPGA XC3S100E-TQ144 Spartan-3E (50 I/O
    pins)
  • Flash memory
  • VGA port
  • Serial RS232 port and USB 2.0 (can be used for
    power supply)
  • 2 displays and 8 LEDs indicators
  • Reduced size for integration

AVNET HW-ADS-XLX-SP3E-EVL100
1293 cm
19
Set-up for the tests
20
Power board (interface)
21
Results
  • Spectrum of the transmitted signal
  • Signal is filtered to cancel the 50 Hz component
    of the LV network (interference) and to eliminate
    the shaped noise spectrum (Sigma Delta D/A)

22
Results
  • Waveform of the received signal

23
Results
  • Slot detection
  • Correlation based on hard decision
  • Scrambling codes have quasi-optimum auto- and
    cross-correlation properties (Gold codes)

24
Summary
  • Matlab 7.0.1
  • System design, cosimulation and verification
  • ISE 7.1
  • FPGA programming (hardware description language -
    VHDL)
  • ModelSim
  • Hardware simulation and verification
  • MultiSim
  • Desing of printed circuit boards (PCB)

25
Conclusions
  • A number of simulation tools are required in the
    process of system desing and prototyping
  • They can operate individually or interface
  • From our experience, simulation results are
    credible
  • Detailed simulation models are required
  • Both hardware and software
  • More results and conclusions will be presented
    during the Final Symposium
  • Contribution to task 3.1 Verification and
    validation
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