ECE 425 VLSI Circuit Design

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ECE 425 - VLSI Circuit Design

• Lecture 4 - Layout Design Rules
• Spring 2005

Prof. John NestorECE DepartmentLafayette
CollegeEaston, Pennsylvania 18042nestorj_at_lafayet
te.edu
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Announcements

• Reading
• Wolf 2.4-2.6

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Where we are...

• Last time
• Transistor Modes of Operation
• More about Wires Vias
• Parasitics
• Today
• Parasitics continued (Lecture 3 pp. 28-40)
• Layout Design Rules Stick Diagrams
• Discuss Lab 3

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Mask Generation

• Mask Design using Layout Editor
• user specifies layout objects on different layers
• output layout file
• Pattern Generator
• Reads layout file
• Generates enlarged master image of each mask
  layer
• Image printed on glass reticle
• Step repeat camera
• Reduces copies reticle image onto mask
• One copy for each die on wafer
• Note importance of mask alignment

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Symbolic Mask Layers

• Key idea
• Reduce layers to those that describe design
• Generate physical layers as needed
• Magic Layout Editor "Abstract Layers
• metal1 (blue) - 1st layer metal (equiv. to
  physical layer)
• Poly (red) - polysilicon (equivalent to physical
  layer)
• ndiff (green) - n diffusion (combination of
  active, nselect)
• ntranistor (green/red crosshatch) - combined
  poly, ndiff
• pdiff (brown) - p diffusion (combination of
  active, pselect)
• ptransistor (brown/red crosshatch) - combined
  poly, pdiff
• contacts combine layers, cut mask

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About Magic

• Scalable Grid for Scalable Design Rules
• Grid distance l (lambda)
• Value is process-dependent l 0.5 X minimum
  drawn transistor length
• Painting metaphor
• Paint squares on grid for each mask layer
• Layers to interact to form components (e.g.
  transistors)

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Mask Layers in Magic

• Poly (red)
• N Diffusion (green)
• P Diffusion (brown)
• Metal (blue)
• Metal 2 (purple)
• Well (cross-hatching)
• Contacts (X)

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Magic User-Interface

• Graphic Display Window
• Cursor
• Box - specifies area to paint
• Command window (not shown)
• accepts text commandspaint polypaint
  redpaint ndiffpaint greenwrite
• prints error status messages

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Layer Interaction in Magic

• Transistors - where poly, diffusion cross
• poly crosses ndiffusion - ntransistor
• poly crosses pdiffusion - ptransistor
• Vias - where layers connect
• Metal 1 connecting to Poly - polycontact
• Metal 1 connecting to P-Diffusion (normal) - pdc
• Metal 1 connecting to P-Diffusion (substrate
  contact) - psc
• Metal 1 connecting to N-Diffusion (normal) - ndc
• Metal 1 connecting to N-Diffusion (substrate
  contact) - nsc
• Metal 1 connecting to Metal 2 - via

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Magic Layers - Example
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Lab 2 - Introduction to Magic

• Preparation
• Read Prof. Stines Magic Tutorial
• Read Magic Tutorials 1 2
• In the Lab
• Use the PCs running Linux - log in with CS
  account or using login ece / password ece
• Do Step by Step Example in Magic Tutorial
• Create a layout for a 3-input NAND gate
• Plot with flea and hand in

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Design Rules

• Motivation Fabrication is not exact
• Too much material - bloat
• Too little material - shrinkage
• Misalignment
• Typical rules
• Minumum size
• Minimum spacing
• Alignment / overlap
• Composition
• Negative features

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Types of Design Rules

• Scalable Design Rules (e.g. SCMOS)
• Based on scalable coarse grid - l (lambda)
• Idea reduce l value for each new process, but
  keep rules the same
• Key advantage portable layout
• Key disadvantage not everything scales the same
• Not used in real life
• Absolute Design Rules
• Based on absolute distances (e.g. 0.75µm)
• Tuned to a specific process (details usually
  proprietary)
• Complex, especially for deep submicron
• Layouts not portable

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SCMOS Design Rules

• Intended to be Scalable
• Original rules SCMOS
• Submicron SCMOS-SUBM
• Deep Submicron SCMOS-DEEP
• Pictorial Summary Book Fig. 2-24, p. 27
• Authoritative Reference www.mosis.org

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SCMOS Design Rule Summary

• Line size and spacing
• metal1 Minimum width3l, Minimum Spacing3l
• metal2 Minimum width3l, Minimum Spacing4l
• poly Minimum width 2l, Minimum Spacing2l
• ndiff/pdiff Minimum width 3l, Minimum
  Spacing3l, minimum ndiff/pdiff seperation10l
• wells minimum width10l, min distance form well
  edge to source/drain5l
• Transistors
• Min width3l
• Min length2l
• Min poly overhang2l

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SCMOS Design Rule Summary

• Contacts (Vias)
• Cut size exactly 2l X 2l
• Cut separation minimum 2l
• Overlap min 1l in all directions
• Magic approach Symbolic contact layer min. size
  4l X 4l
• Contacts cannot stack (i.e., metal2/metal1/poly)
• Other rules
• cut to poly must be 3l from other poly
• cut to diff must be 3l from other diff
• metal2/metal1 contact cannot be directly over
  poly
• negative features must be at least 2l in size
• CMP Density rules (AMI/HP subm) 15 Poly, 30
  Metal

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Design Rule Checking in Magic

• Design violations displayed as error paint
• Find which rule is violated with "drc why Poly
  must overhang transistor by at least 2 (MOSIS
  rule 3.3)

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Stick Diagrams

• Key idea "Stick figure cartoon" of a layout
• Useful for planning layout
• relative placement of transistors
• assignment of signals to layers
• connections between cells
• cell hierarchy

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Stick Diagrams (cont'd)
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Stick Diagram Examples
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Stick Diagram Examples
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Example Layout / Stick Diagram

• Create a layout for a NAND gate given
  constraints
• Use minimum-size transistors
• Assume power supply lines pass through cell
  from left to right at top and bottom of cell
• Assume inputs are on left side of cell
• Assume output is on right side of cell
• Optimize cell to minimize width
• Optimize cell to minimize overall area

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Layout Example
Exterior of Cell
Circuit Diagram.
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Example - Stick Diagrams
Alternatives - Pull-up Network
Circuit Diagram.
Pull-Down Network (The easy part!)
Complete Stick Diagram
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Example - Magic Layout

• Overall Layout 52 X 16

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Lab 3 - Layout from Stick Diagrams

• Design an AOI-22 gate
• Logic function (AB CD)
• Follow the constraints given in the lab handout
• Start with a stick diagram
• Create a Magic layout
• Minimize height and overall area
• Hand in flea plot marked with dimensions at end
  of lab
• Hand in Technical Memorandum w/ plot in lab
  next week.

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Coming Up

• Hierarchical Layout
• Review Levels of Abstraction
• More Layout CAD Tools Extraction, LVS
• ASIC Layout Styles