Decode

1
Decode

• Decode instruction bits and allocate stack

2
Issue Instruction

• Load operands from registers

3
ALU and MAC

• ALU pipeline
• Shift bits
• Arithmetic and logical operations
• Save state and registers
• 3-stage MAC
• Can issue a 16x16 operation per cycle
• Processed with ALU pipeline

4
Data Cache Access

• Map memory address
• Data cache load/store requires 2 cycles

5
Writeback

• Write results of instructions to designated
  memory, cache, or register

6
8-Stage Pipeline
Diagram by Devereau7