COMPUTER SYSTEM OVERVIEW

1
COMPUTER SYSTEM OVERVIEW

• Chapter 1

2
What is an Operating System?

• A system that provides users with an abstraction
  of the hardware a virtual computer.
• Interfaces between user and machine.
• On one side, it manages the hardware resources.
• On the other side, it provides a (more or less)
  user-friendly interface.

3
Computer System Overview

• Basic components of a computer system
• Interrupts
• Multiprogramming
• Memory hierarchy
• I/O communication techniques

4
Top Level Components

• Processor (CPU)
• Main memory
• holds program code and data
• I/O modules
• control movement of data between CPU and devices
  e.g. disk, keyboard, monitor
• System buses
• carry signals between different components
• address, data control buses

5
CPU Registers

• Control and Status Registers
• Used by CPU and OS generally not available to
  user programs
• Examples program counter (PC), instruction
  register (IR), program status word (PSW)

6
Control and Status Registers

• Program Counter (PC)
• Contains address of next instruction to be
  fetched
• Instruction Register (IR)
• Contains the instruction most recently fetched
• Program Status Word (PSW)
• Condition codes
• Interrupt enable/disable
• Supervisor/user mode

7
User-Visible CPU Registers

• Used by the operating system and user programs
• Data registers temporarily store values from
  memory
• Address registers
• contain all or part of a main memory address.
• used to calculate effective addresses

8
User Visible Data Registers

• Data registers may be called accumulators
• Many machine language operations require the
  operand to be in a register.
• Temporary results are stored in registers to
  avoid a (slow) memory reference.

9
User Visible Address Registers

• Contain a base address or an offset to be added
  to a base address during effective address
  computation.
• Index usually treated as an offset
• Segment for segmented memory systems, designates
  the base address of the current segment.
• Stack points to top of system stack

10
Instruction Execution

• Von Neumann architecture/stored program computers
• Instruction cycle the processing required to
  execute one instruction
• The cycle repeats until the computer halts for
  some reason.

11
Basic Instruction Cycle

• CPU fetches next instruction from memory.
• Instruction is decoded and executed.
• Program counter (PC) is automatically incremented
  to get address of next instruction.

12
Four Categories of Instructions

• Processor-memory copy data from CPU register to
  memory, or vice versa
• Processor-I/O transfer data from processor to an
  I/O module, or vice versa.
• Process data perform an arithmetic or logical
  operation (add, compare, etc.)
• Control alter normal (sequential) flow of
  instruction execution.

13
Interrupts

• What is an interrupt?
• Why interrupts are needed
• Interrupts and the instruction cycle
• Interrupt processing
• Classes of interrupts
• Interrupts and multiprogramming

14
Interrupts

• An interrupt is a signal to the CPU from some
  other module in the system.
• For example, when an I/O operation completes, the
  I/O module will interrupt.
• The CPU will then interrupt its normal flow of
  control to process the interrupt.
• Interrupts improve CPU efficiency.
• The following example illustrates why.

15
Control Flow Without Interrupts

• User program runs (1) until WRITE instruction
  transfers control to the I/O program.
• I/O program prepares I/O module for printing (4).
• CPU waits for I/O command to complete, which may
  take a long time.
• I/O program finishes in (5) and report status of
  operation.
• User program resumes executing (until next
  WRITE).

16
Why Interrupts are Needed

• In the previous example, the CPU has to wait for
  I/O to complete.
• It would be more efficient if the processor could
  continue to execute instructions while the device
  executes in parallel.
• Interrupts make this possible.

17
Instruction Cycle with Interrupts

• An additional step is added to the instruction
  execution cycle to accommodate the
  test-for-interrupt operation.

18
Interrupts

• Suspend the normal sequence of execution

19
Control Flow with Interrupts

• User program executes WRITE. Control branches to
  an I/O program,which issues the I/O command. (4)
• I/O program returns control to user application
• User code executes during I/O operation no
  waiting
• User program interrupted (x) when I/O operation
  is done. CPU branches to interrupt handler
• (2b) Execution of user code resumes

20
Interrupt Processing

• Interrupt processing is asynchronous - comes at
  unpredictable points in program execution.
• The interrupted program must not be affected, so
  its state must be temporarily saved and later
  restored
• Full description of processing is in the text.

21
Interrupt Processing

• Hardware steps are automatic details vary
  slightly according to CPU architecture.
• Software steps exact details depend on nature of
  interrupt
• Interrupts allow devices and CPU to run in
  parallel.

22
Classes of Interrupts

• Caused by an execution error, such as divide by
  zero or illegal memory reference.
• Timers can be set by the OS. When the timer
  interrupts, its time to perform some function.
• Signals normal or abnormal completion of an I/O
  operation. Generated by the associated I/O
  controller.
• Example power failure

• Program
• Timer
• I/O
• Hardware failure

23
Interrupts and I/O

• A program cannot always continue after issuing
  I/O command. Example
• Program issues a disk read and needs disk data
  before continuing
• If the user program continues to run during the
  I/O operation, it might not get correct answers
  since its data wont be available.

24
Multiprogramming

• The solution is to have other programs available
  to keep the CPU busy.
• While one user program waits for input, the
  processor can execute commands from another
  program.
• In this way, two programs can sometimes run in
  about the same time it would take one of them.

25
Multiprogramming

• Definition Management of multiple programs
  within a single processor system
• After CPU issues an I/O command, it can switch to
  execute another program (no waiting)
• A second program runs during I/O operation
• When I/O is completed, interrupt handler may (or
  may not) switch back to the first program

26
Multiprogramming

• Multiprogramming allows a computer to run several
  programs concurrently.
• Multiprogramming improves processor efficiency by
  keeping the CPU busy during I/O.
• Interrupts are essential to support
  multiprogramming.

27
THE MEMORY HIERARCHY

• Characteristics
• Caching
• Locality of Reference
• Hit Ratio

28
Memory Hierarchy

• Three characteristics of memory access time,
  cost, capacity.
• Fast memory is expensive
• Slow memory is cheap
• The problem how can we build a large memory
  with good performance at a reasonable price?

29
The Solution Cache Memory

• The cache contains a subset of the information in
  main memory.
• Small, expensive, fast
• Stores current data instructions
• CPU operates out of the cache

30
How Cache Works

• It is invisible to OS and user programs -
  interacts with other memory management hardware
• On a memory reference the processor first checks
  if the word (or byte) referenced is in cache (a
  hit)
• If not found in cache (a miss), a block of memory
  containing the word is moved to the cache

31
Caching Hierarchy

• Cache Levels (fastest to slowest)
• L1 (primary)
• L2 (probably)
• L3 (maybe)
• Cache levels mirror memory hierarchy.
• Question why does caching work?

32
Locality of Reference

• As a program executes, its memory references to
  instructions and data tend to cluster in the same
  area of memory
• e.g. instructions in a loop, data in an array
• Once a word is referenced it will probably be
  referenced again and words in the same area of
  memory (locality) will be referenced also.
• Consequently, its worthwhile to bring that block
  of memory into cache.

33
The Hit Ratio

• Hit ratio fraction of accesses where referenced
  address is in cache
• T1 access time for fast memory (e.g. cache)
• T2 access time for slow memory (e.g. memory)
• T2 gtgt T1
• When hit ratio is close to 1 the average access
  time is close to T1

34
Formula for Effective System Access Time

• For a two-level memory (M1 M2), letH hit
  ratioT1 access time to M1 (e.g., cache)T2
  access time to M2 (e.g., memory)
• Then Ts (system access time) isTs H T1 (1
  - H) (T1 T2)

35
Importance of Caching

• Cache misses gt extra memory reference
• Read (write) latency time to read (write) memory
• Memory access time gtgt CPU speed

36
Extensions of Caching

• Disk cache (disk buffer)
• Part of main memory is used to temporarily to
  hold data from the disk
• Locality of reference also applies here.
• Disk caches are managed by the OS (file system)
  instead of the hardware.
• Disks may have onboard caches to reduce need for
  seeks

37
I/O COMMUNICATION

• Programmed I/ORequires the processor to poll for
  I/O completion and directly transfer the data
  between memory and the I/O module. No parallelism
• Interrupt-driven I/OCPU must still transfer
  data, one word at a time, but can do other things
  while the operation is being performed. More
  parallelism
• DMA (Direct Memory Access)Provides the most
  parallelism, therefore the best performance.

38
Figure 1.19 three Techniques for Input of a
Block of Data
39
DMA I/O

• CPU issues an I/O request to a DMA module
  (separate module or incorporated into I/O module)
• DMA module transfers a block of data directly to
  or from memory (without going through CPU)
• An interrupt is sent when the task is complete
• The CPU is only involved at the beginning and end
  of the block transfer - not after every word
• If the CPU and DMA module clash over memory bus
  access, priority is given to the DMA module.