???? IC ?? ? ?? Lecture 1

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???? IC ?? ? ??Lecture 1

• Seungjun Lee
• Information Electronics Eng.
• Ewha Womans University

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Topics

• Hardware Description Language (HDL)
• Levels of Abstraction
• VLSI Design Flow
• Features of HDL
• History of Verilog
• Verilog Simulation

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Introduction

• Hardware Description Language(HDL)
• a language that can describe the functionality
  and timing of hardware circuits
• Verilog, VHDL, etc
• Simulator
• software which reads the HDL and emulates the
  hardware described by the HDL
• Verilog-XL, NC-Verilog from Cadence
• VCS from Synopsys
• ModelSim from Mentor
• SILOS from SimuCAD

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Levels of Abstraction
Algorithm/ Specification
(RTL Register Transfer Logic)
VLSI Implementation
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32-bit RISC Processor Design
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Schematic Entry
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Schematic Entry gt HDL

• module aoi_gate (o, a1, a2, b1, b2)
• input a1, a2, b1, b2
• output o
• wire o1, o2
• and g1(o1, a1, a2)
• and g2(o2, b1, b2)
• nor g3(o, o1, o2)
• endmodule

words in bold are Verilog keywords
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Various HDL Descriptions

• module aoi_gate (o, a1, a2, b1, b2)
• input a1, a2, b1, b2
• output o
• wire o1, o2
• assign 1 o o1 o2
• assign 1 o2 b1 b2
• assign 1 o1 a1 a2
• endmodule

module aoi_gate (o, a1, a2, b1, b2) input a1,
a2, b1, b2 output o wire o1, o2
nor g3(o, o1, o2) and g2(o2, b1,
b2) and g1(o1, a1, a2) endmodule
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C/C vs. Verilog
C/C Verilog
Purpose Programming language Hardware description language
Execution mode Sequential execution Fully parallel execution
Description order Description order makes difference Description order makes no difference in most times
Notion of time No notion of time Notion of time (e.g. gate delay)
Data type int, long, float, double, char, string nets, registers integer, real for simulation purpose
Execution environment C compiler (Visual C, gcc, ...) Software simulator (Verilog-XL, vcs, ModelSim, Silos, ...)
Debugging environment Debugger (Visual C, dbx, gdb, ...) Simulator waveform viewer (signalscan, ModelSim, ...)
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Simulating a Module
Test bench
module aoi_gate
monitor outputs
generate inputs
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Test bench

• A module that is used to simulate target designs
• It has no inputs and no outputs.
• It will have the design instantiated in it.
• It will generate necessary test signals and apply
  them to the instantiated design.
• The outputs from the design are brought back to
  the test bench for further analysis.
• The test benches are mostly done at the
  behavioral level.
• may contain high level constructs that are not
  usually allowed in hardware modules
• e.g. integer, real, initial, wait, fork, join,
  ...

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Test bench Example

• module top
• reg a1, a2, b1, b2
• wire out
• initial begin
• a1 1 a2 0 b1 1 b2 1
• 5 a2 1
• 2 a1 0 b1 0
• 3 a1 1
• end
• aoi_gate g0(out, a1, a2, b1, b2)
• initial monitor (time, a1 b, a2 b, b1
  b, b2 b, out b, a1, a2, b1, b2, out)
• initial 15 finish
• endmodule

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Simulation Results in ModelSim
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History of Verilog

• 1981
• a CAE software company called Gateway Design
  Automation was founded by Prabhu Goel
• 1983
• Gateway released the Verilog Hardware Description
  Language known as Verilog HDL or simply Verilog
  together with a Verilog simulator
• 1985
• the language and simulator were enhanced and the
  new version of the simulator was called Verilog-XL

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History of Verilog

• 1983 to 1987
• the Verilog-XL simulator gained a strong foothold
  among advanced, high-end designers mainly because
  it was fast, especially at the gate level and
  could handle designs in excess of 100,000 gates
• 1987
• another startup company, Synopsys, began to use
  the proprietary Verilog behavioral language as an
  input to their synthesis product
• the IEEE released the VHDL standard, drawing
  attention to the possibilities of top-town design
  using a behavioral HDL and synthesis
• December 1989
• Cadence bought Gateway

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History of Verilog

• Early 1990
• Cadence split the Verilog HDL and the Verilog-XL
  simulator into separate products, and then
  released the Verilog HDL to the public domain
• Cadence did this partly to compete with VHDL,
  which was a nonproprietary HDL, and mostly
  because Verilog users wanted to share models and
  knowledge about Verilog, which was not easy with
  a proprietary language
• Open Verilog International (OVI) was formed to
  control the language specification
• OVI is an industry consortium comprised of both
  Veirlog users and CAE vendors

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History of Verilog

• 1990
• nearly all ASIC foundries supported Verilog and
  most used Verilog-XL as a golden simulator
• the golden simulator is the one that an ASIC
  vendor will use to sing-off a chip against, and
  guarantee that a manufactured chip will meet the
  same timing as that of the simulated model
• 1993
• of all designs submitted to ASIC foundries in
  this year, 85 were designed and submitted using
  Verilog (Source EE Times)
• 1995
• the Verilog language was reviewed and adopted by
  the IEEE as IEEE Standard 1364-1995

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Verilog vs.VHDL
Verilog VHDL
Relatively low level of complexity Relatively high level of complexity Offers more flexibility
Suited for lower level design (RTL and below) Suited for system level design
Fast simulations Slower simulations