14:332:331 Computer Architecture and Assembly Language Fall 2006 Week 1

1
14332331Computer Architecture and Assembly
LanguageFall 2006Week 1

• Adapted from Dave Pattersons UCB CS152 slides
  and
• Mary Jane Irwins PSU CSE331 slides

2
Course Administration

• Instructor Yanyong Zhang
• yyzhang_at_ece.rutgers.edu
• Core 518
• Hours TF 1015 1115 am
• TAs TBD
• Labs Everyone will be using your ece account.
• Texts Computer Organization and Design The
  Hardware/Software Interface, Third Edition,
  Patterson and Hennessy
• VHDL Starters Guide, Yalamanchili

3
Course Administration

• Course web page http//www.ece.rutgers.edu/yyzhan
  g/fall06
• Please check the course web page regularly (at
  least once before class) for announcements,
  assignments, and more importantly, lecture notes.
• Class mailing list ece331_f06_at_rams.rutgers.edu
• By default, I will use your eden account. If you
  prefer another email account, please send me
  emails.
• Please post emails on this list only when you
  want to talk to the whole class. If you only want
  to talk to the instructor, or a TA, please send
  him/her individual emails.
• I will be using the list to distribute the
  announcements and answer some common questions.
• I will send test messages before Fridays
  lecture. Please talk to me on Friday if you
  havent got anything.
• WebCT is available for you to check your grades
  and conduct group discussion. Please do not
  expect the instructor to participate.

4
Convention

• Please check your email and the course web page
  regularly.
• Every class
• First 10-15 minutes, review of last class
• Students will be randomly picked to answer
  questions
• Class participation will be based on this
• Discussion-oriented
• Instructor vs. TA vs. students
• Instructors are responsible for answering
  questions related to the lectures and exams
• TAs are responsible for answering questions
  related to homework, projects, and grades
• If TAs cannot answer the students, they will
  contact the instructor directly.

5
Course Goals and Structure

• Fundamentals of assembly language programming
• MIPS assembler programming using the spim system
• Introduction to the major components of a
  computer system. To bridge the gap between high
  level programming and low level digital design.
• VHDL design simulation using the Synopsys VSS
  tools
• Prerequisite (required)
• 14332231 Digital Logic Design
• 14332252 Programming Methodology
• Corequisites
• 14332333 Computer Architecture Lab

6
spim Assembler and Simulator

• spim is a self-contained assembler and simulator
  for the MIPS R2000/R3000
• It provides a simple assembler, debugger and a
  simple set of operating system services
• It implements both a simple, terminal-style
  interface and a visual windowing interface
• Available as
• xspim on unix
• installed on the Sun machines in EE bldg,
  /usr/local/spim/bin/xspim
• PCSpim on Windows
• can be downloaded and installed on your own PC
  from
• www.cs.wisc.edu/larus/spim.html
• Sorry, there is no Macintosh version of spim

7
vhdl Analyzer and Simulator

• VSS is Synopsyss VHDL system simulator
• It provides a vhdl analyzer that translates vhdl
  code into the binary required by the vhdl
  simulator
• It provides a vhdl simulator and a source code
  debugger with a graphical user interface for
  monitoring the simulation
• It provides a waveform viewer for observing the
  results of the simulation as signal waveforms
• Available as
• vhdlan (text based) or gvan (graphical)
• vhdlsim (text based) or vhdldbx (graphical)
• waves
• The entire (almost) Synopsys tool set is
  installed on the Sun machines in the EE bldg

8
Grading Information

• Grade determinates
• Midterm Exam 1 21
• Midterm Exam 2 23
• Final Exam 26
• Homework Assignments 10
• In-class pop quizzes 15
• Class Participation 5
• Please let me know about exam conflicts ASAP

9
Grading Policies

• Assignments will be submitted via email (mostly)
  and must be turned in by 500pm on the due date.
  No late assignments will be accepted.
• All the assignments should be completed
  individually. Duplicate assignments will receive
  duplicate grades of zero. Second offenses will
  result in a final course grade of F.
• Grades will be posted on the WebCT
• See TAs about grading questions on the
  assignments
• see instructor (me) about grading questions on
  the exams

10
About 14332333

• 14332333 will start from next week
• Section 01  Time M 1200-300 PM  
• Section 02 Time T 140-440 PM
• Section 03 Time W 320-620 PM

11
Heads Up

• This weeks material
• Course introduction
• Reading assignment PH 1.1 through 1.3 and A.9
  through A.10
• Reminders
• 14332333 will start from next week
• Question/comments about the system go to
  help_at_ece.rutgers.edu questions
  about the programming assignments go to the
  course TA
• Next weeks material
• Introduction to MIPS assembler
• Reading assignment - PH 3.1 through 3.3, 3.4, and
  3.7

12
What You Should Already Know

• How to write, compile and run programs in a
  higher level language (C, C, Java, )
• How to create, organize, and edit files and run
  programs on Unix
• How to represent and operate on positive and
  negative numbers in binary form (twos
  complement, sign magnitude, etc.)
• Logic design
• How to design combinational and sequential
  components (Boolean algebra, logic minimization,
  technology mapping, decoders and multiplexors,
  latches and flipflops, registers, mealy/moore
  finite state machines, state assignment and
  minimization, etc.)
• How to use a logic schematic capture and
  simulation tool (e.g., LogicWorks)

13
Below the Program

• High-level language program (in C)
• swap (int v, int k)
• (int temp
• temp vk
• vk vk1
• vk1 temp
• )
• Assembly language program (for MIPS)
• swap sll 2, 5, 2
• add 2, 4,2
• lw 15, 0(2)
• lw 16, 4(2)
• sw 16, 0(2)
• sw 15, 4(2)
• jr 31
• Machine (object) code (for MIPS)
• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• . . .

14
Below the Program

• High-level language program (in C)
• swap (int v, int k)
• (int temp
• temp vk
• vk vk1
• vk1 temp
• )
• Assembly language program (for MIPS)
• swap sll 2, 5, 2
• add 2, 4,2
• lw 15, 0(2)
• lw 16, 4(2)
• sw 16, 0(2)
• sw 15, 4(2)
• jr 31
• Machine (object) code (for MIPS)
• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• . . .

15
Advantages of Higher-Level Languages

• Higher-level languages
• As a result, very little programming is done
  today at the assembler level

• Allow the programmer to think in a more natural
  language and for their intended use (Fortran for
  scientific computation, Cobol for business
  programming, Lisp for symbol manipulation, )
• Improve programmer productivity more
  understandable code that is easier to debug and
  validate
• Improve program maintainability
• Allow programmers to be independent of the
  computer on which they are developed (compilers
  and assemblers can translate high-level language
  programs to the binary instructions of any
  machine)
• Emergence of optimizing compilers that produce
  very efficient assembly code optimized for the
  target machine

16
Machine Organization

• Capabilities and performance characteristics of
  the principal Functional Units (FUs)
• e.g., register file, ALU, multiplexors, memories,
  ...
• The ways those FUs are
  interconnected
• e.g., buses
• Logic and means by which
  information flow between FUs
  is controlled
• The machines Instruction Set Architecture (ISA)
• Register Transfer Level (RTL) machine description

17
Major Components of a Computer
18
Computer Types

• Notebook computer
• Sony Vaio, IBM Thinkpad, etc
• Mobile users
• Desktop
• Dell Dimension, Dell OptiPlex
• Most widely used in everyday life
• Workstation
• Dell Precision, Sun Blade, IBM IntelliStation
• Same dimensions as desktop computers
• High-resolution graphics I/O capability, more
  computational power
• servers supercomputers
• HP Integrity Superdome, IBM eServer
• Computing power and storage

19
Computer Organization
20
Instruction vs. Data

• void main () // instruction
• int a,b,c // data
• c a b // instruction

• Instructions (machine instructions)
• Govern the transfer of information within a
  computer (e.g., load, store)
• Specify the arithmetic and logic operations to be
  performed (e.g., add, sub, mul)
• Data
• Operands of the instruction
• Both instructions and data are in binary format

21
Input Device Inputs Object Code

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Processor
Devices
Control
Input
Memory

• Input devices
• Keyboard
• Mouse
• Network
• Joysticks, trackballs, etc

Datapath
Output
22
Object Code Stored in Memory
Memory
Processor
Devices

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Control
Input
Datapath
Output
23
Memory Unit to store the program

• Primary storage fast memory that operates at
  electronic speed
• Programs must be stored in fast memory when they
  are being executed
• The memory contains a large number of
  semiconductor storage cells, each containing a
  bit
• The unit of memory access is a byte or a word,
  not a bit
• To provide easy access to any byte/word, a
  distinct address is associated with each byte
  location
• The number of bits in each word is called word
  length of the computer. That is also the length
  of instructions.
• RAM random access memory. Access time to any
  location is uniform
• Memory hierarchy L-1 cache, L-2 cache, main
  memory
• Secondary storage
• Magnetic disks, tapes, optical disks

24
How to execute a program?

• Sequential execution

Decode
25
Processor Organization

• Control needs to have the
• Ability to input instructions from memory
• Logic and means to control instruction sequencing
• Logic and means to issue signals that control the
  way information flows between datapath components
• Logic and means to control what operations the
  datapaths functional units perform
• Datapath needs to have the
• Components - functional units (e.g., adder) and
  storage locations (e.g., register file) - needed
  to execute instructions
• Components interconnected so that the
  instructions can be accomplished
• Ability to load data from and store data to memory

26
Instruction Fetch

• How do you know which instruction next?
• PC (Program Counter)
• Where to store PC? (disk, memory, cache,
  register)
• How to update PC? (sequential, branch)

27
Processor Fetches an Instruction
Processor fetches an instruction from memory
PC
Memory
Processor
Devices

• 000000 00000 00101 0001000010000000
• 000000 00100 00010 0001000000100000
• 100011 00010 01111 0000000000000000
• 100011 00010 10000 0000000000000100
• 101011 00010 10000 0000000000000000
• 101011 00010 01111 0000000000000100
• 000000 11111 00000 0000000000001000

Control
Input
Datapath
Output
28
Control Decodes the Instruction
Control decodes the instruction to determine what
to execute
Processor
Devices
Control

• 000000 00100 00010 0001000000100000

Memory
Input
Datapath
Output
29
Datapath Executes the Instruction
Datapath executes the instruction as directed by
control
Processor
Devices
Control

• 000000 00100 00010 0001000000100000

Memory
Input
Datapath

• contents Reg 4 ADD contents Reg 2
• results put in Reg 2

Output
30
Output Data Stored in Memory
At program completion the data to be output
resides in memory
Memory
Processor
Devices
Control
Input

• 00000100010100000000000000000000
• 00000000010011110000000000000100
• 00000011111000000000000000001000

Datapath
Output
31
Output Device Outputs Data
Processor
Devices
Control
Input
Memory
Datapath
Output

• 00000100010100000000000000000000
• 00000000010011110000000000000100
• 00000011111000000000000000001000

32
Hardware/Software Interface

• Instruction set architecture includes everything
  programmers need to know to make a binary program
  to work
• Instruction
• Arithmetic and Logic Unit (ALU), registers, etc

hardware
33
The Instruction Set Architecture
software
instruction set architecture
hardware
The interface description separating the software
and hardware.
34
MIPS R3000 Instruction Set Architecture
Registers

• Instruction Categories
• Load/Store
• Computational
• Jump and Branch
• Floating Point
• coprocessor
• Memory Management
• Special

R0 - R31
PC
HI
LO

• 3 Instruction Formats all 32 bits wide

OP
rs
rd
sa
funct
rt
OP
rs
rt
immediate
OP
jump target
Q How many already familiar with MIPS ISA?
35
How Do the Pieces Fit Together?
Application
Operating
System
Compiler
Firmware
Instruction Set Architecture
I/O system
Instr. Set Proc.
Memory system
Datapath Control
Digital Design
Circuit Design

• Coordination of many levels of abstraction
• Under a rapidly changing set of forces
• Design, measurement, and evaluation

36
How Do the Pieces Fit Together?
Application
Operating
System
Compiler
Firmware
Instruction Set Architecture
I/O system
Instr. Set Proc.
Memory system
Datapath Control
Digital Design
Circuit Design

• Coordination of many levels of abstraction
• Under a rapidly changing set of forces
• Design, measurement, and evaluation