Complexity Analysis of a Massively Parallel Boolean Satisfiability Implication Circuit

1

• Complexity Analysis of a Massively Parallel
  Boolean Satisfiability Implication Circuit

Ph.D. Defense By Mark J. Boyd Chair
Tracy Larrabee Reader Andrea Di Blas
Reader Richard Hughey
2
Significant and Novel Research

• Analyzed O(mn) parallelism for SAT
• Showed unroutability of FPGA approach
• Demonstrated floorplanned solution

3
Overview

• Synopsis of the research
• Boolean satisfiability (SAT)
• Previous FPGA parallel approaches
• Zhong (Princeton) instance-specific
• Unroutable with claimed resources
• My floorplanned approach
• ELVIS single chip
• PRISCILA multi-chip
• Conclusion

4
Overview - Research

• Research interests
• Boolean satisfiability
• Fundamental open problem with currently
  exponential runtime
• FPGAs
• Parallel applications
• Rapid prototyping
• Dynamic rerouting
• I implemented a regular floorplan methodology
• ELVIS
• Single chip design
• Easily and quickly loaded
• PRISCILA
• Multi-chip design explicitly showing external
  routing scalability

5
Overview - Motivations

• FPGA approach has long compile times
• Field Programmable Custom Computing Machines
  Conference
• We showed routing problem unscalable
• We presented a regular generalized layout
• Need to evaluate wide clauses in parallel
• GRASP and zchaff software
• Clause addition helps scalable speedup GOOD!
• Wide clauses take time to evaluate BAD!

6
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• k3, maximum clause width
• n4, number of variables
• m5, number of clauses

7
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• k3, maximum clause width
• n4, number of variables
• m5, number of clauses

8
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• k3, maximum clause width
• n4, number of variables (A,B,C,D)
• m5, number of clauses

9
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• k3, maximum clause width
• n4, number of variables
• m5, number of clauses

10
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• k3, maximum clause width
• n4, number of variables
• m5, number of clauses
• L13, number of literals

11
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

12
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TBC)(AB)(BC)(ABC)(ACD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

13
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TBC)(FB)(BC)(ABC)(ACD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

14
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TBC)(FB)(BC)(FBC)(ACD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

15
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TBC)(FB)(BC)(FBC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

16
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFC)(FB)(BC)(FBC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

17
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFC)(FT)(BC)(FBC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

18
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFC)(FT)(TC)(FBC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

19
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFC)(FT)(TC)(FFC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

20
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFF)(FT)(TC)(FFC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

21
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFF)(FT)(TT)(FFC)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

22
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFF)(FT)(TT)(FFT)(FCD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

23
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFF)(FT)(TT)(FFT)(FFD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

24
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

25
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• T
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

26
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• T T
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

27
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• T T T
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

28
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• T T T T
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

29
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• T T T T T
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

30
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• T T T T T TRUE
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

31
Boolean satisfiability (SAT)

• But wouldnt it be nice if all of these
  operations happened simultaneously?
• (ABC)(AB)(BC)(ABC)(ACD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment

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Boolean satisfiability (SAT)

• But wouldnt it be nice if all of these
  operations happened simultaneously?
• T T T T T TRUE
• (TFF)(FT)(TT)(FFT)(FFT)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment
• Well get there soon

33
Boolean satisfiability (SAT)

• What is a transitive implication?
• (ABC)(AB)(BC)(ABC)(ACD)
• B1 is a partial truth assignment

34
Boolean satisfiability (SAT)

• What is a transitive implication?
• (ABC)(AF)(BC)(ABC)(ACD)
• B1 is a partial truth assignment

35
Boolean satisfiability (SAT)

• What is a transitive implication?
• (ABC)(AF)(BC)(ABC)(ACD)
• B1 implies A0 because A must now be
  assigned 0 to make the clause true

36
Boolean satisfiability (SAT)

• What is a transitive implication?
• (ABC)(TF)(BC)(ABC)(ACD)
• B1 implies A0

37
Boolean satisfiability (SAT)

• What is a transitive implication?
• (FBC)(TF)(FC)(ABC)(ACD)
• B1 implies A0

38
Boolean satisfiability (SAT)

• What is a transitive implication?
• (FBC)(TF)(FC)(ABC)(ACD)
• B1 implies A0,C0

39
Boolean satisfiability (SAT)

• What is a transitive implication?
• (FBC)(TF)(FT)(ABC)(ACD)
• B1 implies A0,C0, called transitive
  implications

40
Boolean satisfiability (SAT)

• Lets restart and try more variables
• (ABC)(AB)(BC)(ABC)(ACD)
• A1,C1 is a partial truth assignment

41
Boolean satisfiability (SAT)

• Lets restart and try more variables
• (ABC)(FB)(BF)(FBF)(ACD)
• A1,C1 is a partial truth assignment

42
Boolean satisfiability (SAT)

• Lets restart and try more variables
• (ABC)(FB)(BF)(FBF)(ACD)
• A1,C1 implies B0,B1

43
Boolean satisfiability (SAT)

• Lets restart and try more variables
• (ABC)(FB)(BF)(FBF)(ACD)
• A1,C1 implies B0,B1 ?
• But thats a contradiction, right?

44
Boolean satisfiability (SAT)

• Lets restart and try more variables
• (ABC)(FB)(BF)(FBF)(ACD)
• A1,C1 implies B0,B1
• Because it results in a contradiction, A1,C1
  cannot be a part of any satisfying assignment

45
Boolean satisfiability (SAT)

• Lets restart and try more variables
• (ABC)(FB)(BF)(FBF)(ACD)(AC)
• A1,C1 implies B0,B1
• Because A1,C1 cannot be a part of any
  satisfying assignment we can add a clause
  forbidding it. DeMorgan (AC) (AC)

46
Boolean satisfiability (SAT)

• But wouldnt it be nice if all of these
  operations happened simultaneously?
• (ABC)(FB)(BF)(FBF)(ACD)(AC)
• A1,C1 implies B0,B1
• Well get there

47
Boolean satisfiability (SAT)

• Lets try a really big problem
• (ABCDG)(ABCEH)(ABDEI)
• (ACDEJ)(BCDEK)(GHIJK)
• A0,B0,C0,D0,E0 implies

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Boolean satisfiability (SAT)

• Lets try a really big problem
• (FFFFG)(FFFFH)(FFFFI)
• (FFFFJ)(FFFFK)(GHIJK)
• A0,B0,C0,D0,E0 implies
• G1,H1,I1,J1,K1

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Boolean satisfiability (SAT)
Boolean satisfiability (SAT)

• Lets try a really big problem
• (FFFFG)(FFFFH)(FFFFI)
• (FFFFJ)(FFFFK)(GHIJK)
• A0,B0,C0,D0,E0 implies
• G1,H1,I1,J1,K1

50
Boolean satisfiability (SAT)

• Lets try a really big problem
• (FFFFG)(FFFFH)(FFFFI)
• (FFFFJ)(FFFFK)(FFFFF)
• A0,B0,C0,D0,E0 implies
• G1,H1,I1,J1,K1, which creates a falsified
  clause

51
Boolean satisfiability (SAT)

• Lets try a really big problem
• (FFFFG)(FFFFH)(FFFFI)
• (FFFFJ)(FFFFK)(FFFFF)
• A0,B0,C0,D0,E0 cannot be a part of any
  satisfying truth assignment, add
• (ABCDE)

52
Boolean satisfiability (SAT)

• 25 operations in parallel?
• (ABCDG)(ABCEH)(ABDEI)
• (ACDEJ)(BCDEK)(GHIJK)
• A0,B0,C0,D0,E0

53
Boolean satisfiability (SAT)

• 25 operations in parallel?
• (FFFFG)(FFFFH)(FFFFI)
• (FFFFJ)(FFFFK)(GHIJK)
• A0,B0,C0,D0,E0 implies
• G1,H1,I1,J1,K1
• Wouldnt THAT be something

54
Boolean satisfiability (SAT)

• 25 operations in parallel?
• (FFFFG)(FFFFH)(FFFFI)
• (FFFFJ)(FFFFK)(GHIJK)
• A0,B0,C0,D0,E0 implies
• G1,H1,I1,J1,K1
• For kO(n)O(m), O(mn) parallelism

55
Boolean satisfiability (SAT)

• For any m, randomly pick m/2 variables for each
  clause
• Append a new unique variable to each clause
• Add one clause with the negations of all the
  appended variables
• A partial assignment of true to the first m
  variables implies all of the appended variables
  true
• Contradicts the final clause

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Boolean satisfiability (SAT)

• 25 operations in parallel?
• (ABCDG)(ABCEH)(ABDEI)
• (ACDEJ)(BCDEK)(GHIJK)
• A problem which supports O(mn) speedup by
  parallel literal evaluation

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Boolean satisfiability (SAT)

• For SOME k-SAT formulas, evaluating all literals
  and clause implications in a single operation
  provides O(mn) parallelism over serial literal
  operations.

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Purpose of parallelism for speedup of SAT

• Calculating transitive implications, Boolean
  Constraint Propagation (BCP)
• Commonly 90 to 99 of the total runtime
• Excellent heuristics of GRASP or zchaff software
  speed up solution
• Addition of wide conflict clauses avoids
  repetitive search
• Avoids evaluating unneeded clauses
• BUTsoftware heuristics still slow for some
  densely connected unsatisfiable problems
• Hole, hgen benchmarks of about 260 variables

59
Parallel FPGA approaches

• Zhong (Princeton) instance-specific mapping of a
  formula to an FPGA
• State machine generates partial assignments to
  send to IMP circuit
• IMP circuit calculates implications and sends
  back results

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Parallel FPGA approaches

• Zhong (Princeton) instance-specific mapping of a
  formula to an FPGA
• Each clause is made into a gate for each variable
• But this is a bipartite graph 2-Level
  Planarization problem NP-hard for arealtO(n )

2
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What is an FPGA?

• An array of logic and memory
• Logic cells (4x4 memory)
• A mesh of routing
• Crossbar switchboxes (4x4) supporting flexible
  interconnect

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Parallel FPGA PR

• Zhong (Princeton) instance-specific mapping
  requires PR
• Each clause is made into a gate for each variable
• But this is a bipartite graph 2-Level
  Planarization problem NP-hard for arealtO(n )

2
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Parallel FPGA PR
1 2 3 4 5 6
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Zhong gate blowup for big k

• Zhong (Princeton) instance-specific mapping of a
  formula to an FPGA
• Wide clause made into gates BIG
• Example
• Clause from hole10
• Even gates grow as O(k m)

2

• (12345678910)

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General Floorplan of ELVIS
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Shift Register Bus Mask

• Eliminate routing problem by
• Routing all variables to all clauses using a bus
• Masking unused variable signals using a shift
  register

67
Shift Register Bus Mask

• Only allows the lines through that are selected
  by the shift register

0
0
0
0
0
1
1
1
1
1
0
0
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Oneact one active encoder

• A multi-bit unary input, two-bit result
• An adder that overflows at 2

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Shift Register Bus Mask
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Example of CEC
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Example of CEC, A1, C1
1
0
0
0
1
0
0
0
1
1
1
0
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Example of VEC, A1, C1
1
1
1
0
1
0
0
0
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Example of VEC, A1, C1
1
1
1
0
1
0
0
0
0
1
0
1
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The other two variables
1
75
Floorplan of CECs and VECs
CECs
VECs
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Partition of CECs and VECs
CECs
VECs
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Board Layout of PRISCILA
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Overview of PRISCILA

• 14 FPGA boards
• Regular wiring with 40 wire ribbon cables
• 12 boards for a 3x4 rectangular array
• 1 board is the FSM
• 1 board to collect data on performance
• 3.1 MHz theoretical maximum
• 1.6 MHz tested

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Cycle Speedup of PRISCILA
Dubois
Pretolani
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Analysis

• Cycles for A-SAT are really complex operations
  (load, load, decrement,store), so not comparable
• Assumed memory latency increases with size of
  problem. Not necessarily true for cached,
  pipelined serial processor
• Used a big (32 var, 48 clause) PRISCILLA for all
  problems. Latency not scaled.

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The Hughey Amendment

• Cycles for A-SAT are really complex operations
  (load, load, decrement,store), so not comparable
• Doesnt matter, just want scalable speedup
• Assumed memory latency increases with size of
  problem. Not necessarily true for cached,
  pipelined serial processor
• Assume perfect pipe/cache, constant access times
• Used a big (32 var, 48 clause) PRISCILLA for all
  problems. Latency not scaled.
• Penalize larger problems by a factor of m (delay)

82
Speedup of PRISCILA
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Rebuttal to Hughey Amendment

• Scalable speedup (between log and linear)
• VS a serial processor of O(1) memory latency!
• Because serial processor is O(mn) operations
• Results arent a proof in themselves (too small)
  but are consistent with previous work

84
How can ELVIS/PRISCILA improve

• Two major improvements
• Use the carry logic in FPGAs for wide functions
• Cycle speeds improved by 100x (250 MHz)
• Resource usage much more efficient
• Design a parallel FSM to drive the implication
  logic faster
• Transitive implications only 90-99 of the total
  time
• Speedups over 10-100 not generally possible
  except for hardest benchmarks

85
What can ELVIS/PRISCILLA do

• Coprocessor for industrial problems
• zchaff extraction of small cores within 2-20 of
  size of the minimal unsatisfiable core.
• PRISCILLA detects unsatisfiable formulas 10-100
  times faster (limited by state machine)
• Place and route, logic minimization, verification
  and testing of circuits and software, airline
  scheduling

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RECAP and Acknowledgments

• Parallel calculation of SAT
• transitive implications
• O(mn) over software
• Instance-specific approaches unscalable
• Negative result
• Scalable floorplanned approach (ELVIS)
• Useful for small unsatisfiable cores
• Any clause width
• Multi-chip (PRISCILLA)
• More speedup from larger problems

Acknowledgements Kevin Klenk for help with
initial state machine design. Doanna Weissgerber
for help with the software loading interface.
NSF funding under CCR-9971172. Xilinx for
devices and ISE software.
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P Parallel Pipelines
90
Pipelined approach

• Zhong time-sliced variables through a pipeline

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EXTRAS
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The Experiment Results

• Average times in seconds to complete all tasks
  for each of the 21 alignments
• Experimental group 1.5 times faster

93
Protein Structure

• Hierarchical Structure
• Goal understand function of protein from primary
  structure
• Sequence of protein relatively easy to obtain

94
Floorplan of the Approach
95
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (AB)(ABC)(BC)(ABD)
• (CD)(BCD)(ACD)(BD)
• k3, maximum clause width
• n4, number of variables
• m8, number of clauses

96
Boolean satisfiability (SAT)

• A k-SAT formula is a Boolean expression in
  conjunctive normal form (CNF)
• (ABC)(AB)(BC)(ABC)(ACD)
• A1, B0, C0, D1 is an easily verified
  satisfying truth assignment
• T T T T T TRUE
• (TFF)(FT)(TT)(FFT)(FFT)

97
Protein Structure
98
Floorplan of the Approach
99
A Critically Unsatisfiable Formula
100
Parallel FPGA approaches
101
Floorplan of the Approach
102
Layers ofVisPad
Independent of RDAG-128H
Dependent on RDAG-128H knowledge