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1
Leakage tolerant Keeper sizing for Dynamic Circuit
Manoj Sinha Advisor Prof. Wayne Burleson
2
Fundamentals of Sizing
Vk

• The keeper sizing is based on the basic
  hypothesis of DC unity gain noise margin.
• For a given dc noise Vn, the keeper M4 is sized
  to attain dc unity gain noise margin.
• The output of the symmetrical static inverter
  will be Vn for unity gain.

M4
Vn
Vout
Vn
M2
Vx
M1

• Vout is determined by equating the current of the
  output static inverter.
• Vk Vn, based on dc unity gain noise margin and
  symmetrical inverter.
• Determine Vx by equating current of M2
  (sub-threshold region) M1 (linear region).
• Equate the current of keeper to the current in M1
  (foot NMOS) to determine the keeper (M4) size.

3
MOSFET Model for Analysis

• Model Equations used
• VDSAT K(VGS VTH)m
• IDSAT (W / Leff) B(VGS VTH)n
• Saturated Region (VDSAT lt VDS)
• IDS IDSAT (1 ? VDS)
• Linear Region (VDSAT gt VDS)
• Ilin IDS 2 (VDS / VDSAT ) (VDS / VDSAT )
• Simulation Calculation error
• Max. error of 8.6 in saturation region
• Max. error of 4.4 in linear region

T. Sakurai A.R. Newton, A Simple MOSFET Model
for Circuit Analysis, in IEEE Trans on Electron
Devices, April 1991
4
PMOS Simulated Calculated result

• Simulation Modeling Error
• Saturation region maximum error of 8.3.
• Linear region maximum error of 12.4

5
Subthreshold Current Modeling

• Model Equations used
• IS IO 10(Vgs Vt) / s
• where Vt Vtlin ?DIBL VDS and s is
  sub-threshold slope
• Vt determination using Constant Current Method
• VGS VTH
• (when IDS reaches normalized value of
• W/Leff 10-7A)
• DIBL (Vtsat - Vtlin ) / (VDS 50mV)
• where Vtlin is measured at VDS 50mV
• Subthreshold slope is measured as the change in
  Vgs for which Ids becomes 10 times on log plot.
• s 130mV at 110C

6
Simulated Calculated result for Subthrehold
Current

• There is an error of 12-14 for the calculated
  the result as compared to the simulated result.

7
Dynamic Circuits Considered for Keeper sizing
M4
M4
Vn
Vn
Vout
Vout
ON
M3
Vn2
Vn1
M2
M3
Vy
Vn1
M2
Vx
Vx
M1
M1
M4
Vn
Vout
Vn2
ON
M3
M5
Vy
Vn1
M2
Vx
M1
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Keeper Sizing Preliminary result
9
Conclusions and Future Work

• There is an accuracy of within 9-12 for sizing
  the keeper based on unity dc gain noise margin.
• This sizing methodology looks promising as it is
  robust and fairly accurate.
• Future work would involve
• More simulations for a range of target noise.
• Simulation results for different circuit
  topologies.
• Develop an algorithm that can take any complex
  dynamic circuit and target dc noise as input and
  generate the keeper size.