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Dynamic Partial Reconfiguration of an FPGA for Computational Hardware Support

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Dynamic Partial Reconfiguration of an FPGA for Computational Hardware Support. A way to make computers faster and more ... ASICs are powerful, not flexible ... – PowerPoint PPT presentation

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Title: Dynamic Partial Reconfiguration of an FPGA for Computational Hardware Support


1
Dynamic Partial Reconfiguration of an FPGA for
Computational Hardware Support
Jens Thorvinger Electroscience Lund Institute of
Technology
  • A way to make computers faster and more powerful

2
Outline
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Introduction
  • Background and Motivation
  • The work
  • Design Considerations
  • Suggested Architecture
  • Methodology
  • Future

3
Introduction
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Background and Motivation

4
The Processor
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Processors are flexible, not powerful
  • A processor is optimized for running all kinds of
    programs and is therefore ineffective since it is
    not optimized for a specific problem.
  • A processor is ineffective since it does
    operations sequentially.

5
Processor Execution
Jens Thorvinger Electroscience Lund Institute of
Technology
  • The graph to the right will be evaluated node by
    node.
  • Ineffective
  • The nodes on a particular level have no data
    dependencies and can be concurrently evaluated

6
The ASIC Application Specific Integrated Circuit
Jens Thorvinger Electroscience Lund Institute of
Technology
  • ASICs are powerful, not flexible
  • An ASIC is optimized for a specific problem and
    therefore not flexible.
  • An ASIC is effective since it can be fully
    parallelized.

7
ASIC Execution
Jens Thorvinger Electroscience Lund Institute of
Technology
  • All the nodes on a particular level can be
    concurrently evaluated

8
The 90 10 Rule
Jens Thorvinger Electroscience Lund Institute of
Technology
  • 90 of the execution is spent in 10 of the code
  • Inner loops in algorithms
  • Computational intense code
  • 10 of the execution is spent in 90 of the code
  • Exceptions
  • User interaction

9
The Idea
Jens Thorvinger Electroscience Lund Institute of
Technology
  • The 10 computational intense code is to be run
    as a hardware mapped configuration in a device
    which i reconfigurable
  • The 90 exception code is run as a normal program
    executing in a processor

10
Physical Integration
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Processor is master and in control

Processor
Memory
11
Reconfigurable Device
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Must have the functionality of an ASIC, yet
    reconfigurable

12
FPGA Field Programmable Gate Array
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Can map any hardware configuration

13
The Work
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Design Considerations
  • Suggested Architecture
  • Methodology

14
The FPGA board used
Jens Thorvinger Electroscience Lund Institute of
Technology
15
Design
Jens Thorvinger Electroscience Lund Institute of
Technology
  • FPGA Xilinx Virtex-II
  • Divide it into several independent modules
  • Connect the modules using a bus

16
Restrictions
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Reconfigurable module full height
  • Module width 8 slices
  • Pins are not global
  • Connect modules through bus macro
  • Clocks are global

17
Restrictions Layout
Jens Thorvinger Electroscience Lund Institute of
Technology
18
Bus Macro
Jens Thorvinger Electroscience Lund Institute of
Technology
  • At reconfiguration, all connections are either
    changed or kept glitch-free
  • A bus macro goes through dedicated physical wires
  • This keeps the bus intact during reconfiguration

19
Bus Macro Layout
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Xilinx bus macro

20
Custom Made Bus Layout
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Custom made bus macro

21
Bus Communication
Jens Thorvinger Electroscience Lund Institute of
Technology
  • The communication is set up as a memory
    communication with address bus, bi-directional
    data bus and control signals
  • The static module is master and the
    reconfigurable are slaves
  • The static module is responsible for setting the
    tri-state buffers of the reconfigurable modules

22
No Simultaneous Writing
Jens Thorvinger Electroscience Lund Institute of
Technology
23
Bus Macro in FPGA_Editor
Jens Thorvinger Electroscience Lund Institute of
Technology
24
Bus Macro in FPGA_Editor
Jens Thorvinger Electroscience Lund Institute of
Technology
25
Bus Macro in FPGA_Editor
Jens Thorvinger Electroscience Lund Institute of
Technology
26
One bit Quadruple
Jens Thorvinger Electroscience Lund Institute of
Technology
27
Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Run the make-bus script
  • A bus spanning across the FPGA is created with
    address bus, bi-directional data bus and control
    signals

28
Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Create top VHDL file
  • The make-bus script created a template top VHDL
    file as well
  • The top VHDL file has all port definitions of all
    reconfigurable modules and the bus macro
  • All reconfigurable modules are calledtemplate
    names(pos1, pos2, pos3...)

top VHDL
29
Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Create top VHDL file
  • Create constraint file
  • Specify the location of the static module, the
    reconfigurable modules and the bus macro

30
Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Create top VHDL file
  • Create constraint file
  • Create static module
  • Create the VHDL code for the static module
  • Run the build script (s)

static VHDL
31
Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Create top VHDL file
  • Create constraint file
  • Create static module
  • Create dummy module
  • Create the VHDL code for the dummy module
  • Run the build script (p)

dummy VHDL
32
Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Create top VHDL file
  • Create constraint file
  • Create static module
  • Create dummy module
  • Create fully assembledconfiguration
  • Run the build script (f)

full .bit file
33
Methodology Third Party Developer
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Create bus macro
  • Create top VHDL file
  • Create constraint file
  • Create reconfigurable modules
  • Run the build script (p)

reconf. VHDL
pos1 .bit file
pos3 .bit file
34
During Execution
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Start up Power on
  • Empty FPGA

35
During Execution
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Start up Power on
  • Initialization
  • Download initial configuration

full .bit file
36
During Execution
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Start up Power on
  • Initialization
  • Download partial configurations when needed

pos3 .bit file
37
The make-bus script
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Creates bus macro
  • Parameters m, a, d
  • m Number of modules
  • a Address bus width
  • d Data bus width
  • Creates a XDL file describing resources reserved
    and logical connections
  • Converts the XDL file to a NMC file
  • Creates a script witch routes the NMC file in
    FPGA_Editor

38
The make-bus script
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Creates bus macro
  • Creates a template top VHDL file
  • Describes the created bus macro and instantiates
    it
  • Describes all reconfigurable module as template
    names (pos1, pos2, pos3...) and instantiates them
  • Has a template static module and template
    external pins and instantiates the template
    static module
  • Instantiates signals and connects all
    instantiated modules with them

39
The build script
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Build static module
  • Parameters s ltvhdl-filegt
  • Synthesizes the top VHDL fileSynthesizes the
    module VHDL file
  • Build static VHDL file into static module
    location
  • Generate a localy place and routed design

40
The build script
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Build static module
  • Build reconfigurable module
  • Parameters p ltposgt ltvhdl-filegt
  • Synthesizes the top VHDL fileSynthesizes the
    module VHDL file
  • Build reconfgiurable VHDL file into pos module
    location
  • Generate a localy place and routed design
  • Generate a .bit file for download

41
The build script
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Build static module
  • Build reconfigurable module
  • Build final assembly
  • Parameters f ltvhdl-filegt
  • Assemble the static place and routed module with
    a dummy module for all locations
  • Generate a full .bit file for download

42
Future
Jens Thorvinger Electroscience Lund Institute of
Technology
  • The next generations

43
First Generation Software improvements
Jens Thorvinger Electroscience Lund Institute of
Technology
  • On chip reconfiguration
  • Module error detection
  • Master reconfigurable modules

44
Second Generation New ASIC
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Identical reconfigurable modules
  • Static module really static
  • Static bus really static
  • Optimizing the FPGA structure
  • Module error detection

45
Third Generation
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Processor FPGA integration

46
Fourth Generation
Jens Thorvinger Electroscience Lund Institute of
Technology
  • World domination...

47
Thank You!
Jens Thorvinger Electroscience Lund Institute of
Technology
  • Questions?
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