Title: Dynamic Partial Reconfiguration of an FPGA for Computational Hardware Support
1Dynamic Partial Reconfiguration of an FPGA for
Computational Hardware Support
Jens Thorvinger Electroscience Lund Institute of
Technology
- A way to make computers faster and more powerful
2Outline
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Technology
- Introduction
- Background and Motivation
- The work
- Design Considerations
- Suggested Architecture
- Methodology
- Future
3Introduction
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- Background and Motivation
4The Processor
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- Processors are flexible, not powerful
- A processor is optimized for running all kinds of
programs and is therefore ineffective since it is
not optimized for a specific problem. - A processor is ineffective since it does
operations sequentially.
5Processor Execution
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Technology
- The graph to the right will be evaluated node by
node. - Ineffective
- The nodes on a particular level have no data
dependencies and can be concurrently evaluated
6The ASIC Application Specific Integrated Circuit
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Technology
- ASICs are powerful, not flexible
- An ASIC is optimized for a specific problem and
therefore not flexible. - An ASIC is effective since it can be fully
parallelized.
7ASIC Execution
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- All the nodes on a particular level can be
concurrently evaluated
8The 90 10 Rule
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- 90 of the execution is spent in 10 of the code
- Inner loops in algorithms
- Computational intense code
- 10 of the execution is spent in 90 of the code
- Exceptions
- User interaction
9The Idea
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- The 10 computational intense code is to be run
as a hardware mapped configuration in a device
which i reconfigurable - The 90 exception code is run as a normal program
executing in a processor
10Physical Integration
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- Processor is master and in control
Processor
Memory
11Reconfigurable Device
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- Must have the functionality of an ASIC, yet
reconfigurable
12FPGA Field Programmable Gate Array
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- Can map any hardware configuration
13The Work
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- Design Considerations
- Suggested Architecture
- Methodology
14The FPGA board used
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15Design
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- FPGA Xilinx Virtex-II
- Divide it into several independent modules
- Connect the modules using a bus
16Restrictions
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- Reconfigurable module full height
- Module width 8 slices
- Pins are not global
- Connect modules through bus macro
- Clocks are global
17Restrictions Layout
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18Bus Macro
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- At reconfiguration, all connections are either
changed or kept glitch-free - A bus macro goes through dedicated physical wires
- This keeps the bus intact during reconfiguration
19Bus Macro Layout
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20Custom Made Bus Layout
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21Bus Communication
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- The communication is set up as a memory
communication with address bus, bi-directional
data bus and control signals - The static module is master and the
reconfigurable are slaves - The static module is responsible for setting the
tri-state buffers of the reconfigurable modules
22No Simultaneous Writing
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23Bus Macro in FPGA_Editor
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24Bus Macro in FPGA_Editor
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25Bus Macro in FPGA_Editor
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26One bit Quadruple
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27Methodology
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Technology
- Create bus macro
- Run the make-bus script
- A bus spanning across the FPGA is created with
address bus, bi-directional data bus and control
signals
28Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
- Create bus macro
- Create top VHDL file
- The make-bus script created a template top VHDL
file as well - The top VHDL file has all port definitions of all
reconfigurable modules and the bus macro - All reconfigurable modules are calledtemplate
names(pos1, pos2, pos3...)
top VHDL
29Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
- Create bus macro
- Create top VHDL file
- Create constraint file
- Specify the location of the static module, the
reconfigurable modules and the bus macro
30Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
- Create bus macro
- Create top VHDL file
- Create constraint file
- Create static module
- Create the VHDL code for the static module
- Run the build script (s)
static VHDL
31Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
- Create bus macro
- Create top VHDL file
- Create constraint file
- Create static module
- Create dummy module
- Create the VHDL code for the dummy module
- Run the build script (p)
dummy VHDL
32Methodology
Jens Thorvinger Electroscience Lund Institute of
Technology
- Create bus macro
- Create top VHDL file
- Create constraint file
- Create static module
- Create dummy module
- Create fully assembledconfiguration
- Run the build script (f)
full .bit file
33Methodology Third Party Developer
Jens Thorvinger Electroscience Lund Institute of
Technology
- Create bus macro
- Create top VHDL file
- Create constraint file
- Create reconfigurable modules
- Run the build script (p)
reconf. VHDL
pos1 .bit file
pos3 .bit file
34During Execution
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- Start up Power on
- Empty FPGA
35During Execution
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- Start up Power on
- Initialization
- Download initial configuration
full .bit file
36During Execution
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- Start up Power on
- Initialization
- Download partial configurations when needed
pos3 .bit file
37The make-bus script
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- Creates bus macro
- Parameters m, a, d
- m Number of modules
- a Address bus width
- d Data bus width
- Creates a XDL file describing resources reserved
and logical connections - Converts the XDL file to a NMC file
- Creates a script witch routes the NMC file in
FPGA_Editor
38The make-bus script
Jens Thorvinger Electroscience Lund Institute of
Technology
- Creates bus macro
- Creates a template top VHDL file
- Describes the created bus macro and instantiates
it - Describes all reconfigurable module as template
names (pos1, pos2, pos3...) and instantiates them - Has a template static module and template
external pins and instantiates the template
static module - Instantiates signals and connects all
instantiated modules with them
39The build script
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- Build static module
- Parameters s ltvhdl-filegt
- Synthesizes the top VHDL fileSynthesizes the
module VHDL file - Build static VHDL file into static module
location - Generate a localy place and routed design
40The build script
Jens Thorvinger Electroscience Lund Institute of
Technology
- Build static module
- Build reconfigurable module
- Parameters p ltposgt ltvhdl-filegt
- Synthesizes the top VHDL fileSynthesizes the
module VHDL file - Build reconfgiurable VHDL file into pos module
location - Generate a localy place and routed design
- Generate a .bit file for download
41The build script
Jens Thorvinger Electroscience Lund Institute of
Technology
- Build static module
- Build reconfigurable module
- Build final assembly
- Parameters f ltvhdl-filegt
- Assemble the static place and routed module with
a dummy module for all locations - Generate a full .bit file for download
42Future
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Technology
43First Generation Software improvements
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- On chip reconfiguration
- Module error detection
- Master reconfigurable modules
44Second Generation New ASIC
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- Identical reconfigurable modules
- Static module really static
- Static bus really static
- Optimizing the FPGA structure
- Module error detection
45Third Generation
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- Processor FPGA integration
46Fourth Generation
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47Thank You!
Jens Thorvinger Electroscience Lund Institute of
Technology