Test Wrapper Designs for the Detection of Signal Integrity Faults on Core External Interconnects of SOCs

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Test Wrapper Designs for the Detection of Signal
Integrity Faults on Core External Interconnects
of SOCs

• Qiang Xu and Yubin Zhang Krishnendu Chakrabarty
  The Chinese University of Hong Kong
  Duke University

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Outline

• Introduction
• Prior work and motivation
• Overshoot detector
• Wrapper design for interconnect SI test
• Experimental results
• Conclusion

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Signal Integrity
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Impact of Technology Scaling
Interconnect
Crosstalk
Serious crosstalk
Shrinking feature size
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Signal Integrity Problem
Signal integrity is a major concern!
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Testing SOC Interconnects
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Typical WOC for Interconnect SI Test

• Simultaneous aggressor transitions in test mode
• Different from functional mode

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Impact of Aggressor Alignment on Crosstalk

• Transition timing of aggressors/victim
  significantly affects signal integrity
• Need for skewed transitions to avoid under-testing

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Prior Overshoot Detector

• Cross-coupled differential amplifier
• Test_Mode signal as control of source current
• Hysteresis property
• Input-dependent detection
• Cannot detect overshoot in all cases!

Source M. Nourani and A. Attarha, TCAD02
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Motivation

• Prior SI test techniques
• simultaneous transitions in test mode may result
  in under-testing.
• cannot detect overshoot in all cases.
• We need
• wrapper input cell that can detect overshoot and
  delay faults in all cases.
• wrapper output cell that can apply skewed
  transitions.

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Proposed Overshoot Detector

• Maintain hysteresis property
• Self-biased amplifier, higher resolution
• Reset mechanism
• Can detect overshoot in all cases

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Comparison of Overshoot Detectors
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Comparison of Overshoot Detectors
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Comparison of Overshoot Detectors
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Wrapper Input Cell

• Equipped with overshoot detector
• One extra FF as delay detector (FF1).

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Wrapper Input Cell

• Equipped with overshoot detector
• One extra FF as delay detector (FF1).
• Save test data

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Wrapper Input Cell

• Equipped with overshoot detector
• One extra FF as delay detector (FF1).
• Save test data
• Shift out result

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Test Strategy I
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Test Strategy I
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Test Strategy I
Functional path
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Test Strategy II
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Test Strategy II
Test path
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Controlled-Delay Element for Skewed-Transition
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Proposed Wrapper Output Cell
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Proposed Wrapper Output Cell
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Experimental Setup

• 90 nm technology with 1V power supply
• 5 mm long victim with 5 aggressors, each coupling
  for a 1 mm length
• On the eighth metal layer with typical parameter

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Experimental Results with Previous WOC
0.556 ns
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Experimental Results with Proposed WOC
with 2 delay paths
with 4 delay paths
0.614 ns
0.595 ns
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Experimental Results with Proposed WOC Cont.
with 6 delay paths
with 8 delay paths
0.622 ns
0.627 ns
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Discussion

• Benefits
• Enhanced signal-integrity fault detection
  capability
• Costs
• DfT area overhead
• test time
• Possible over-testing

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Conclusion

• Signal integrity is a major concern for todays
  SoC interconnects
• We have proposed novel test wrappers that
• Detect all kinds of overshoots
• Apply skewed-transitions for aggressors/victim
  groups
• Have moderate overhead

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Q A