IEEE 2015 VLSI HIGH-SPEED AND ENERGY-EFfiCIENT CARRY SKIP ADDER OPERATING UNDER.pptx

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HIGH-SPEED AND ENERGY-EF?CIENT CARRY SKIP ADDER
OPERATING UNDER A WIDE RANGE OF SUPPLY VOLTAGE
LEVELS
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ABSTRACT

• A carry skip adder (CSKA) is
  designed that has a higher speed yet lower energy
  consumptioncompared with the conventional one.
  The speed enhancement isachieved by applying
  concatenation and incrementation schemesto
  improve the ef?ciency of the conventional CSKA
  (Conv-CSKA)structure. In addition, instead of
  utilizing multiplexer logic, theproposed
  structure makes use of AND-OR-Invert (AOI)
  andOR-AND-Invert (OAI) compound gates for the
  skip logic. Thestructure may be realized with
  both ?xed stage size and variablestage size
  styles, wherein the latter further improves the
  speedand energy parameters of the adder.

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• Finally, a hybrid variablelatency extension of
  the proposed structure, which lowers thepower
  consumption without considerably impacting the
  speed,is presented. This extension utilizes a
  modi?ed parallel structurefor increasing the
  slack time, and hence, enabling further
  voltagereduction. The proposed structures are
  assessed by comparingtheir speed, power, and
  energy parameters with those of otheradders using
  a 45-nm static CMOS technology for a wide rangeof
  supply voltages.

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EXISTING METHOD

• Recently, the near-threshold region has been
  consideredas a region that provides a more
  desirable tradeoff pointbetween delay and power
  dissipation compared with that of thesubthreshold
  one, because it results in lower delay
  comparedwith the subthreshold region and
  signi?cantly lowersswitching and leakage powers
  compared with the superthresholdregion.

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PROPOSED METHOD

• The key contributions are
• 1) Proposing a modi?ed CSKA structure by
  combining theconcatenation and the incrementation
  schemes to theconventional CSKA (Conv-CSKA)
  structure for enhancingthe speed and energy
  ef?ciency of the adder. Themodi?cation provides
  us with the ability to use simplercarry skip
  logics based on the AOI/OAI compound gates
  instead of the multiplexer.
• 2) Providing a design strategy for constructing
  anef?cient CSKA structure based on analytically
  expressionspresented for the critical path delay.

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• 3) Investigating the impact of voltage scaling on
  theef?ciency of the proposed CSKA structure (from
  thenominal supply voltage to the near-threshold
  voltage).
• 4) Proposing a hybrid variable latency CSKA
  structurebased on the extension of the suggested
  CSKA, byreplacing some of the middle stages in
  its structure with a PPA.

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ADVANTAGES

• 1. High speed
• 2. Lower power delay product