mosfet

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NT 2005 MOLECULAR AND NANOELECTRONICS
MOSFET
BY, A. POOJA SHUKLA 1821310006
M. Tech (I year)
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INTRODUCTION TO TRANSISTOR

• In 1947 by John Bardeen, Walter Brattain and
  William Shockley the transistor revolutionized
  the field of electronics
• A transistor is a semiconductor device used to
  amplify and switch electronic signals and
  electrical power.
• It is composed of semiconductor material with at
  least three terminals for connection to an
  external circuit.
• The transistor is the fundamental building block
  of modern electronic devices.

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TYPES OF TRANSISTOR

• BJT
• FET
• MOSFET
• JFET

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FET TERMINALS SYMBOL
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BJT AND FET
BJT
FET
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WHAT IS MOSFET.???

• The metaloxidesemiconductor field-effect
  transistor (MOSFET, MOS-FET, or MOS FET) is a
  transistor used for amplifying or switching
  electronic signals.

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MOSFET
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MOSFET TERMINALS
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TYPES OF MOSFET

• n - MOS FET
• p MOS FET
• CMOS FET

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MOSFET TERMINALS SYMBOL
D
D
G
G
S
Channel
S
Depletion
NMOS
Enhancement
NMOS
D
D
G
G
B
S
S
NMOS with
PMOS
Enhancement
Bulk Contact
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MOSFET STRUCTURE

• This device is symmetric, so either of the n
  regions can be source or drain.

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INTO TO FABRICATION..!!!

• Photolithography (photo)
• Process of transferring pattern on mask to
  photoresist layer on wafer surface (pre-pattern
  the chip)
• Etching
• Process of permanently removed the unwanted part
  of design on wafer surface to get the desired
  pattern
• Diffusion
• Process of introducing dophant layer by movement
  of dophant atoms from high concentration to low
  concentration area at high temperature
• Ion implantation
• Process of introducing dophant layer by
  bombardment of high energy dophant ion in high
  electric field chamber
• Oxidation
• Process of growing thick or thin SiO2 layer
  depend on oxide application
• CMP
• Process to physically grind flat to have a
  planar surface for better exposure at photo
  process.

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MOSFET Transistor Fabrication Steps
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Building A MOSFET Transistor Using Silicon
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It is done. Now, how does it work?
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MOSFET OPERATION
Step 1 Apply Gate Voltage
SiO2 Insulator (Glass)
Gate
Source
Drain
5 volts
holes
N
N
electrons
P
electrons to be transmitted
Step 3 Channel becomes saturated with
electrons. Electrons in source are able to flow
across channel to Drain.
Step 2 Excess electrons surface in channel,
holes are repelled.
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N-MOSFET

• 4 electrical terminals
• Source
• Drain
• Gate
• Substrate
• Connected to Gnd
• Source and drain are only different in their
  interpretation
• Terminal with lower voltage is the source (by
  convention)
• Simplified symbol omits the substrate

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N-MOSFET

• P-type substrate

• N-type dopant for Source Drain

• Inversion layer is formed to conduct electricity

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N-MOSFET

• NMOS Behavior
• When Gate (VG) is high (i.e. 1) the NMOS
  transistor acts as a closed switch
• When VG 0, the NMOS transistor is an open switch

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P-MOSFET

• Same 4 electrical terminals
• Source
• Drain
• Gate
• Substrate
• Connected to VDD
• Again, source and drain are only different in
  their interpretation
• Terminal with higher voltage is the source (by
  convention)
• Simplified symbol omits the substrate

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P-MOSFET

• N-type substrate

• P-type dopant for Source Drain

• Inversion layer is formed to conduct electricity

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P-MOSFET

• PMOS Behavior
• When Gate (VG) is low (i.e. 0) the PMOS
  transistor acts as a closed switch
• When VG 1, the PMOS transistor is an open switch

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CMOSFET PROCESS FLOW
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CMOSFET

• A combination of both NMOS PMOS technology

• Most basic example inverter

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CMOS FABRICATION PROCESSwell formation

• Start with clean p-type substrate (p-type wafer)

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CMOS FABRICATION PROCESSwell formation

• Grow epitaxy layer (made from SiO2) as mask layer
  for well formation

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CMOS FABRICATION PROCESSwell formation
Well will be formed here

• By photolithography and etching process, well
  opening are made
• photolithography and etch processes are shown
  in next slides

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CMOS FABRICATION PROCESS
photoresist

• Photoresist coating (C)
• Masking and exposure under UV light(E)
• Resist dissolved after developed (D)
• Pre-shape the well pattern at resist layer

Si02
P-substrate
UV light
mask
Opaque area
P-substrate
Transparent area
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ETCHING

• Removing the unwanted pattern by wet etching
• Resist clean
• Desired pattern formed

P-substrate
P-substrate
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CMOS FABRICATION PROCESSwell formation
Phosphorus ion

• Ion bombardment by ion implantation
• SiO2 as mask, uncovered area will exposed to
  dophant ion

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CMOS FABRICATION PROCESSisolation formation
Thick oxide

• Increase SiO2 thickness by oxidation at high
  temperature
• Oxide will electrically isolates nmos and pmos
  devices

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CMOS FABRICATION PROCESStransistor making
pmos will be formed here
nmos will be formed here
LOCOS (isolation structure)

• By photolithography and etching process, pmos and
  nmos areas are defined

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CMOS FABRICATION PROCESStransistor making
Gate oxide

• Grow very thin gate oxide at elevated temperature
  in very short time

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CMOS FABRICATION PROCESStransistor making
polysilicon

• Deposit polysilicon layer

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CMOS FABRICATION PROCESStransistor making
gate

• Photolithography (photo) and etching to form gate
  pattern

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CMOS FABRICATION PROCESStransistor making
Arsenic ion
photoresist

• Photo process to define the nmoss active (source
  and drain) area and VDD contact
• Ion implantation with Arsenic ion for n dophant.
• Photoresist and polisilicon gate act as mask

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CMOS FABRICATION PROCESStransistor making
VDD contact
source
drain

• Nmoss Source and drain with VDD contact
  formation
• Resist removal

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CMOS FABRICATION PROCESStransistor making
Boron ion
photoresist

• Photo process to define the GND contact and
  pmoss active area (source and drain)
• Ion implantation with boron ionto have p dophant
• Photoresist and gate act as mask

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CMOS FABRICATION PROCESStransistor making
GND contact
Pmoss drain
Pmos source

• Pmoss source and drain formation with GND
  contact
• Resist removal

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CMOS FABRICATION PROCESSinterconnection
SiO2

• Deposit SiO2 layer through out wafer surface

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CMOS FABRICATION PROCESSinterconnection
contact

• Photo and etching process to make contact

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CMOS FABRICATION PROCESSinterconnection
Metal 1

• Metal 1 deposition throughout wafer surface

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CMOS FABRICATION PROCESSinterconnection

• Photo and etching processes to pattern
  interconnection

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Mask Layout
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Mask Layout
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Mask Layout
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Mask Layout
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THANK YOU.!!!