The PIC 16F84A. This table gives details about what each o

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Clark UniversityComputer Science DepartmentCSCI
140 Computer OrganizationIntroduction to
PICInstruction Set ArchitecturePart 2 - The
Hardware
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Where to Get More Information

• These slides provide only the basic information
  you need. Theres so much more youll need to
  look up to really understand all this. I
  recommend the following
• Bates ? Chapter 8 of our Text
• The description of the 16F84A as given at
  PIC16F84A.pdf
• The Microchip website contains lots of examples
  of code. www.microchip.com
• And of course the web everything is only a
  Google away.

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The PIC 16F84A
Were going to be looking at the architecture of
ONE of the PIC processors. There are many of
them!! The 16F84 is a relatively simple example.
It has a limited number of features, but
everything it does have is carried over to more
complex chips.
This pin diagram is the easiest way to see what
each of the output pins can do. Table 1-1 shown
later gives a somewhat more detailed, view but
the picture here is simple.
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The PIC 16F84A

• High Performance RISC CPU Features
• Only 35 single word instructions to learn
• All instructions single-cycle except for program
  branches which are two-cycle
• Operating speed DC - 20 MHz clock input
• DC - 200 ns instruction cycle
• 1024 words of program memory
• 68 bytes of Data RAM
• 64 bytes of Data EEPROM
• 14-bit wide instruction words
• 8-bit wide data bytes
• 15 Special Function Hardware registers
• Eight-level deep hardware stack
• Direct, indirect and relative addressing modes

• Peripheral Features
• 13 I/O pins with individual direction control
• High current sink/source for direct LED drive
• Special Microcontroller Features
• 10,000 erase/write cycles Enhanced FLASH Program
  memory typical. (You can program the device
  10,000 times.)
• 10,000,000 typical erase/write cycles EEPROM Data
  memory typical.
• EEPROM Data Retention gt 40 years. (You can turn
  the power on/off and the data will still be
  there.)
• In-Circuit Serial Programming (ICSP) - via
• two pins. (You can program the device right in
  the circuit.)

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The PIC 16F84A
This is a simple generalized picture.
This is how the 16F84 really looks.
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The PIC 16F84A
This table gives details about what each of the
hardware pins is used for.
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The PIC 16F84A
MEMORY ORGANIZATION There are two memory blocks
in the PIC16F84A. These are the program memory
and the data memory. Each block has its own bus,
so that access to each block can occur during
the same oscillator cycle. Program Memory
Organization The PIC16FXX has a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16F84A, the first 1K x
14 (0000h-03FFh) are physically implemented as
seen in the Figure. This is space for 1024
instructions! The RESET vector is at 0000h and
the interrupt vector is at 0004h.
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The PIC 16F84A
Data Memory Organization The data memory is
partitioned into two areas The Special Function
Registers (SFR) area, The General Purpose
Registers (GPR) area. The SFRs control the
operation of the device. Instructions MOVWF and
MOVF can move values from the W register to any
location in the register file (F), and
vice-versa. Data memory is partitioned into two
banks which contain the general purpose registers
and the special function registers. Bank 0 is
selected by clearing the RP0 bit (STATUSlt5gt).
Setting the RP0 bit selects Bank 1. Each Bank
extends up to 4Fh (80 bytes). The first 12
locations of each Bank are SFR. The remaining 68
locations are GPR. Some SFRs can be accessed
in either Bank, some can only be reached in a
particular Bank. We use the banksel instruction
to choose the bank we want to use.
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The PIC 16F84A
Special Function Registers
This picture could be intimidating when you first
look at it, but you will get used to it.
Were going to talk about only some of these
registers.
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PIC 16F84A
STATUS REGISTER The STATUS register contains the
arithmetic status of the ALU, the RESET status
and the bank select bit for data memory.
The banksel instruction manipulates this bit.
The Z bit is set when an instruction produces a
zero result.
The C bit is set when an overflow.
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PIC 16F84A
I/O PORTS Some pins for these I/O ports are
multiplexed with an alternate function for the
peripheral features on the device. This means the
pin can used either for I/O OR for something else
(but not both at the same time.) PORTA and TRISA
Registers PORTA is a 5-bit wide, bi-directional
port. The corresponding data direction register
is TRISA. Setting a TRISA bit ( 1) will make the
corresponding PORTA pin an input (i.e., put the
corresponding output driver in a Hi-Impedance
mode). Clearing a TRISA bit ( 0) will make the
corresponding PORTA pin an output (i.e., put the
contents of the output latch on the selected
pin). Reading the PORTA register reads the
status of the pins, whereas writing to it will
write to the port latch. All write operations are
read-modify-write operations. Therefore, a write
to a port implies that the port pins are read.
This value is modified and then written to the
port data latch. PORTB and TRISB
Registers PORTB operates in much the same way as
PORTA, except that all 8 pins can be configured
as I/O.
IO Ports
Notice in the Figure how the I/O pin can be
configured as either input or output.
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TRISA and TRISB are configuration registers.
Their task is to define if the Port A and Port B
pins on the chip are treated as inputs or outputs.
PIC 16F84A
Heres some example code It assumes that the
PORTA and PORTB pins are all configured as I/O so
theres no need to use the OPTION Register.
We want to set PortA to have its bits 03 as
inputs and bit 4 as output We want to set
PortB to have its bits 02 as outputs and bits
37 as input An input is represented by a 1
in the appropriate TRIS- bit. Initialize
bsf STATUS, RP0 This is
equivalent to banksel 1 In the 16F84A,
PortA only has 5 bits bits 57 always read back
as 0 movlw 0x0F movwf TRISA movlw
0xF8 movwf TRISB bcf STATUS, RP0
This is equivalent to banksel 0
clrf PORTA Initialize
as no voltage out clrf PORTB
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PIC 16F84A
What does it mean when the spec says that the
pins are multiplexed with other functions?? It
means that these pins CAN be used as
Input/Output, OR they can be configured to
handle other types of functions. More about
these other functions later.
What do some of these words mean??
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PIC 16F84A
Interrupts

• The PIC16F84A has 4 sources or events that can
  cause an interrupt
• External interrupt RB0/INT pin an electrical
  signal is exerted on the pin.
• TMR0 overflow interrupt the timer has been
  started and then completes its count.
• PORTB change interrupts (pins RB7RB4) - One of
  these pins changes from low to high or high to
  low, and thus an interrupt is signaled.
• Data EEPROM write complete interrupt the
  program started a EEPROM write and then went to
  do something else, and the interrupt occurred
  when that write completed.
• None of these events will cause an interrupt
  unless they are configured to do so.
• The interrupt control register (INTCON) holds all
  the relevant information. It
• records individual interrupt requests in flag
  bits
• it contains the individual and global interrupt
  enable bits.
• The return from interrupt instruction, RETFIE,
  exits interrupt routine as well as sets the GIE
  bit, which re-enables interrupts.
• When an interrupt is responded to,
• the GIE bit is cleared to disable any further
  interrupt,
• the return address is pushed onto the stack
• and the PC is loaded with 0004h which should
  point to code for the interrupt handler.

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PIC 16F84A
Interrupts
The global interrupt enable bit, GIE, enables (if
set) all unmasked interrupts or disables (if
cleared) all interrupts. Individual interrupt
types can be enabled / disabled through their
corresponding enable bits in INTCON register.
These are the enable bits for the various
interrupts.
After an interrupt has occurred, the interrupt
handler can check these bits to determine which
interrupt has occurred.
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PIC 16F84A
Interrupts
As part of Configuration, you must set/clear this
bit.

• We will be using two of these interrupts.
• External Interrupt on RB0/INT PIN
• Edge triggered either rising if INTEDG bit is
  set, or falling if INTEDG bit is clear.
• When a valid edge appears on the RB0/INT pin,
  the INTF bit (INTCONlt1gt) is set.
• This interrupt can be disabled by clearing
  control bit INTE (INTCONlt4gt).
• Flag bit INTF must be cleared in software via
  the Interrupt Service Routine before re-enabling
  this interrupt.
• DATA EEPROM INTERRUPT
• At the completion of a data EEPROM write cycle,
  flag bit EEIF (EECON1lt4gt) will be set.
• The interrupt can be enabled/disabled by
  setting/clearing enable bit EEIE (INTCONlt6gt)

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Context Saving During Interrupts During an
interrupt, only the return PC value is saved on
the stack. Typically, users wish to save key
register values during an interrupt (e.g., W
register and STATUS register). This is
implemented in software. The code in The
Example stores and restores the STATUS and W
registers values. The user defined registers,
W_TEMP and STATUS_TEMP are the temporary storage
locations for the W and STATUS registers values.
PIC 16F84A
Interrupts
SAVING STATUS AND W REGISTERS IN RAM PUSH
MOVWF W_TEMP Copy W to TEMP
register, SWAPF STATUS, W Swap
status to be saved into W MOVWF
STATUS_TEMP Save status to STATUS_TEMP
register ISR Interrupt Service
Routine should configure Bank as
required POP SWAPF
STATUS_TEMP,W Swap nibbles in STATUS_TEMP
register and
place result into W MOVWF STATUS
Move W into STATUS register
(sets bank to original state)
SWAPF W_TEMP, F Swap nibbles in
W_TEMP and put in W_TEMP SWAPF W_TEMP, W
Swap nibbles in W_TEMP and put into W
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PIC 16F84A
EEPROM Memory
DATA EEPROM MEMORY The EEPROM data memory is
readable and writable during normal
operation. This memory is not directly mapped in
the register file space you cant address it
the way you can regular data registers or regular
program memory. It is indirectly addressed
through the Special Function Registers. There
are four SFRs used to read and write this memory.
These registers are EECON1 contains
configuration and status information. EECON2 --
(not a physically implemented register) EEDATA
-- holds the 8-bit data for read/write EEADR
-- holds the address of the EEPROM location
being accessed The PIC16F84A has 64 bytes of
data EEPROM with addresses 0h - 3Fh.
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PIC 16F84A
EEPROM Memory
Can check here that write finished
Enables a write to EEPROM
Starts the write
Starts the Read from EEPROM
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PIC 16F84A
EEPROM Memory
This is an example of code to read from the
EEPROM To read a EEPROM location, the user
must write the desired address to the EEADR
register and then set the control bit RD. banksel
EEADR Aim at bank 0 movlw
Starting_Addr This is the starting address to
use in the EEPROM movwf EEADR Put
that address so the read can find it. banksel
EECON1 Aim at bank 1 bsf EECON1,
RD Define the action as a read banksel
EEDATA Aim at bank 0 movf EEDATA,
W Put the data from EEPROM into the W
register
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PIC 16F84A
EEPROM Memory
This is an example of code to write to the
EEPROM To write a EEPROM location, the user
must write the desired address to the EEADR
register and the data to the EEDATA register.
And then there must be this exact sequence to
write each byte. movlw Starting_Addr This
is the starting address to use in the
EEPROM movwf EEADR Put that
address so the write can find it. movlw
DataToBeWritten movwf EEDATA banksel INTCON
Aim at bank 1 bcf INTCON, GIE
Disable interrupts so we dont mess with
sequence bsf EECON1, WREN Enable a
write movlw 0x55 This is just
what the rules say! movwf EECON2
Write the 0x55 here movlw 0xAA
This is just what the rules say! movwf EECON2
Write the 0xAA here bsf EECON1,
WR Define the action as a write start
it bsf INTCON, GIE Enable
interrupts Wait for the EEIF bit to be set
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PIC 16F84A
Indirect Addressing
Indirect Addressing INDF and FSR Registers The
INDF register is not a physical register.
Addressing INDF actually addresses the register
whose address is contained in the FSR register
(FSR is a pointer). This is indirect addressing.
EXAMPLE 2-1 INDIRECT ADDRESSING Register
file 05 contains the value 10h Register file
06 contains the value 0Ah Load the value 05
into the FSR register A read of the INDF
register will return the value of 10h
Increment the value of the FSR register by one
(FSR 06) A read of the INDF register now
will return the value of 0Ah. Reading INDF
itself indirectly (FSR 0) will produce 00h.
Writing to the INDF register indirectly results
in a no-operation (although STATUS bits may be
affected).
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PIC 16F84A
Indirect Addressing
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example
2-2. EXAMPLE 2-2 HOW TO CLEAR RAM USING
INDIRECT ADDRESSING movlw
0x20 initialize pointer movwf FSR
to RAM NEXT clrf INDF This ACTUALLY
clears the address pointed
to by FSR incf FSR inc pointer
btfss FSR,4 all done? goto
NEXT NO, clear next CONTINUE YES,
continue An effective 9-bit address is obtained
by concatenating the 8-bit FSR register and the
IRP bit (STATUSlt7gt), as shown in Figure 2-3.
However, IRP is not used in the PIC16F84A.
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PIC 16F84A
Indirect Addressing
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PIC 16F84A
In our assembly code, we have a line like this
__CONFIG _CP_OFF _WDT_OFF _RC_OSC This must
be set for each program (it can be done by MPLAB
also). It tells the chip some of the fundamental
configuration that should be done. Note in this
example how the configuration line matches up
with the Register.