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Counters

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... D8.3. Counters. Divide-by-8 Counter. Behavioral Counter in Verilog ... Behavioral Counter in Verilog. Counter using One-Hot State Machine. 3-Bit Counter ... – PowerPoint PPT presentation

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Title: Counters


1
Counters
  • Discussion D8.3

2
Counters
  • Divide-by-8 Counter
  • Behavioral Counter in Verilog
  • Counter using One-Hot State Machine

3
Divide-by-8 Counter
A state diagram for a divide by 8 counter
4
Divide-by-8 Counter
A state-transition table
5
Divide-by-8 Counter
6
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
0
1
1
1
1
D2
D2 Q2 Q1 Q0 Q2 Q1 Q2 Q0
7
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
D1
D1 Q1 Q0 Q1 Q0
8
Divide-by-8 Counter
Q1 Q0
00
01
11
10
Q2
1
1
0
1
1
1
D0
D0 Q0
9
Divide-by-8 Counter
A Divide by 8 counter Circuit using D Flip-flops
10
module DFF (D, clk, clr, Q) input clk wire
clk input clr wire clr input D wire D
output Q reg Q always _at_(posedge clk or
posedge clr) if(clr 1) Q lt 0 else Q lt
D endmodule
11
module count3 ( Q ,clr ,clk ) input clr wire
clr input clk wire clk output 20 Q
wire 20 Q wire 20 D assign D2
Q2 Q1 Q0 Q2 Q1
Q2 Q0 assign D1 Q1 Q0
Q1 Q0 assign D0 Q0 DFF
U2(.D(D2), .clk(clk), .clr(clr), .Q(Q2)) DFF
U1(.D(D1), .clk(clk), .clr(clr), .Q(Q1)) DFF
U0(.D(D0), .clk(clk), .clr(clr),
.Q(Q0)) endmodule
12
count3 Simulation
13
Counters
  • Divide-by-8 Counter
  • Behavioral Counter in Verilog
  • Counter using One-Hot State Machine

14
3-Bit Counter
Behavior
always _at_(posedge clk or posedge clr) begin
if(clr 1) Q lt 0 else Q lt Q 1 end
15
counter3.v
module counter3 (clk, clr, Q ) input clr wire
clr input clk wire clk output 20 Q
reg 20 Q // 3-bit counter always
_at_(posedge clk or posedge clr) begin if(clr
1) Q lt 0 else Q lt Q 1
end endmodule
Asynchronous clear
Output count increments on rising edge of clk
16
counter3 Simulation
17
Recall Divide-by-8 Counter
Use Q2, Q1, Q0 as inputs to a combinational
circuit to produce an arbitrary waveform.
18
Example
State Q2 Q1 Q0 D2 D1 D0 y
s0 0 0 0 0 0 1 1 s1 0 0 1 0 1 0
1 s2 0 1 0 0 1 1 0 s3 0 1 1 1
0 0 0 s4 1 0 0 1 0 1 0 s5 1 0 1
1 1 0 1 s6 1 1 0 1 1 1 0 s7 1 1
1 0 0 0 1
y Q2 Q1 Q2 Q0
19
Counters
  • Divide-by-8 Counter
  • Behavioral Counter in Verilog
  • Counter using One-Hot State Machine

20
One-Hot State Machines
Instead of using the minimum number of flip-flops
(3) to implement the state machine, one-hot
encoding uses one flip-flop per state (8) to
implement the state machine.
21
Why use One-Hot State Machines?
Using one-hot encoding or one flip-flop per state
(8) will normally simplify the combinational
logic at the expense of more flip-flops.
Let's see how for the 3-bit counter
22
One-Hot Encoding
Present state Next state
State Q2 Q1 Q0 D07
Think of each state as a flip-flop
s0 0 0 0 s1 s1 0 0 1 s2 s2 0 1
0 s3 s3 0 1 1 s4 s4 1 0 0
s5 s5 1 0 1 s6 s6 1 1 0 s7 s7 1
1 1 s0
Di si-1
This is just a ring counter!
23
3-bit Counter
State Q2 Q1 Q0
s0 0 0 0 s1 0 0 1 s2 0 1 0
s3 0 1 1 s4 1 0 0 s5 1 0
1 s6 1 1 0 s7 1 1 1
Q2 s4 s5 s6 s7
Q1 s2 s3 s6 s7
Q0 s1 s3 s5 s7
24
module cnt3hot1(clk,clr,Q) input clk input
clr output 20 Q wire 20 Q reg 07
s // 8-bit Ring Counter always _at_(posedge
clk or posedge clr) begin if(clr 1) s lt
8'b10000000 else begin s0 lt
s7 s17 lt s06 end end // 3-bit
counter assign Q2 s4 s5 s6
s7 assign Q1 s2 s3 s6
s7 assign Q0 s1 s3 s5
s7 endmodule
25
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