Robust Mixedsignal Design in Smartpower IC Processes

1
Robust Mixed-signal Designin Smart-power IC
Processes

• R. GillonAMI Semiconductors BelgiumISIE05 SS8
  Power ICs

2
Smart-power ICs ?

• On-board intelligence
• Power handling

• On-board intelligence
• State-machine / logic
• Micro-processor
• Memory ROM, RAM, EEPROM, OTP
• Communication interfaces
• Transmitters, receivers, protocol engines,
• Power handling
• Drivers transistors, diodes
• Sensing Control
• Analogue and conversion circuitry
• Protections
• ESD, EMC, over-temperatures,

3
Smart-power IC !

• Process
• Components
• Isolation schemes
• Interconnects
• PDK
• Models
• Symbols
• Pcells
• Verification
• IP blocks
• Memories
• Digital libraries
• Analogue blocks

4
Robust Mixed-signal Design

• Process
• Components
• Isolation schemes
• Interconnects
• PDK
• Models
• Symbols
• Pcells
• Verification

How to engineer the design-system to enable /
favour robust design practices ?
5
Robust Mixed-signal Design

• B. Gilbert in Trade-offs in analog Circuit
  Design
• the art of anticipating, identifying and
  systematically nulling sensitivities of critical
  performance specifications to variances in the
  manufacturing process and the circuit's
  environment
• Sources of variability (chip-centric universe)
• Intrinsic Variations inherent to the chip
  fabrication, the selected architecture
• Extrinsic Perturbations interaction of the
  chip with a variable environment

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Intrinsic variations

• Process variations
• Die-to-die
• Intra-die (process-induced gradients)
• Component mismatch
• Noise
• Intrinsic noise (semiconductor physics)
• Activity noise (induced random signals)
• Component aging
• Electrical (over-)stress
• Temperature gradients
• Qualification level (process, components)

7
External Perturbations

• Better solved by other means (than IC design)
• Eg moisture
• Not quantifiable, but can be minimizedby
  appropriate measures during IC design
• Eg Mechanical stress degrading transistor
  matching
• Can be quantified and designed for
• Temperature effects
• EMC
• ESD events
• Standardised accidental pulses (eg automtive
  Shaffner)
• Latch-up

8
Process Design Kit ?
9
Overview of Robustness Tools
Internal Variations
Ext. Perturbations
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Managing Electrical Stress Risks

• Introducing different voltage ratings
• For famillies of nets (through labelling)
• For diffused pockets (tubs)
• Formal management of connectivity of components,
  tubs, etc. according to ratings
• DRC rules on nets and pins
• Electrical rule check at schematics level
• Safe-operating area flagging during simulation

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Managing Component Aging Risks

• Static approach or guard-banding
• The life-times under constant stress are
  extracted
• Models issue safe-operating area messages
  according to selected target life-times
• Covers most basic needs

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Managing Component Aging Risks

• Static approach or guard-banding
• The life-times under constant stress are
  extracted
• Models issue safe-operating area messages
  according to selected target life-times
• Covers most basic needs
• Computation of dynamic aging
• Determination of aging rate
• Computation of parameter shifts according to age

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Managing Process Variations

• Die-to-die variations
• Study distributions of key electrical parameters
• Determine dominant modes of variations
  (correlations)

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Managing Process Variations

• Die-to-die variations
• Study distributions of key electrical parameters
• Determine dominant modes of variations
  (correlations)
• Identify correlation groups
• Build sets of corners for each correlation group
• Alternatively provide process Monte-Carlo models
• Modelling paradox
• Statistical data is available in electrical
  parameters
• ETest parameters are not model parameters
• Either repeat extraction many times or build
  special mapping techniques

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Managing External Perturbations

• Electro-Magnetic Compatibility
• Standards for Emission and Susceptibility
  simulations
• Typically from low frequency till 1GHz
• Dielectric transition frequencies of silicon
  substrate
• Redistribution of current filaments in metals not
  properly modelled in most EM simulation tools
  (avoid to solve electric and magnetic fields in
  the conductors).
• Need to assess realism of EMC simulations
  comparing impedance levels at tip of package lead

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Managing External Perturbations

• Testing ESD protection strategy
• Smart-power ICs can have very complex interface
• Many different supply levels
• IO pins with different voltage ratings
• Very large number of pins
• Wide variety of ESD protection cells
• Tool for testing topology of ESD protection
  scheme
• Drop-in replacement of all component models by
  simplified breakdown models
• Forcing of static current in IO pins
• Detection of current paths through simulation
• Flagging of breakdowns outside of ESD protection
  cells
• Extension to detect risks of dynamic failures
• Completed by specific DRC check and generic LVS

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Managing Learning Processes

• Road-map for Smart-power technologies
• Progressive introduction of new features to meet
  the needs and timings of different markets
• Consumer
• Automotive, Aero, Military
• Medical
• Several nested feedback loops
• Tools to support / channel feedback
• Helpdesk systems
• Tracking of qualification status at component
  level
• Quality systems Waivering systems for rule
  violations,

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Conclusions

• Stimulate robustness by construction
• Tackle risks as early as possible in the design
  process
• Favor analytical approaches w.r.t. predefined
  push-button solution
• Efficiency and flexibility of solutions is
  critical
• Enabling robustness requires holistic approach to
  PDK engineering
• ROBUSPIC projects is addressing key topics in
  enabling methodologies for robust design

19
Acknowledgements

• 6th framework program (IST) for funding of the
  ROBUSPIC program
• Partners in ROBUSPIC