PIDS TWG Report on the ITRS Roadmap issues December 6, 2000

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PIDS TWG Report on the ITRS Roadmap
issuesDecember 6, 2000
Participants J. P. Bruines (Philips-Europe), M.
Yoshimi (Toshiba-Japan), D. H. Lee
(Samsung-Korea), P. M. Zeitzoff (International
SEMATECH-USA), J. Y. C. Sun (TSMC-Taiwan)
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Outline

• 2000 update
• Novel Devices Table
• Key 2001 issues
• Summary

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2000 Update, PIDS Modifications

• Sped up scaling of MPU physical gate length (Lg)
• Lg specification pulled in by one year, but only
  through 2001
• Other rows (Vdd, Tox, Ioff, etc.) pulled in by
  one year, for consistency
• In response to IRC recommendations and products
  shipped/announced
• IRC recommendation one year pull-in til 2005
  and beyond
• PIDS did not do pull-in beyond 2001
• Too many issues for 2000 update, particularly for
  gate dielectric
• ASIC Lg same as MPU
• 1999 ITRS MPU Lg lt ASIC Lg

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Key PIDS Table Modifications 2000
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Impact of Lg Pull In Beyond 2001
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2000 Update, PIDS Modifications (cont.)

• DRAM specifications unchanged (DRAM half
  pitchgttechnology node)
• Inadequate time to make changes per IRC
  recommendations to scale more rapidly
• Key issue for 2001 ITRS sped up scaling
• Other Modifications
• MPU/ASIC Physical Gate Length (Lg) defined
  as-etched, final length at bottom of gate
  electrode
• New separate ORTC Litho specifications for
  gate length in photoresist
• Relatively minor clarifications, corrections,
  updates

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Novel Devices Tables

• Novel Devices tables added to Roadmap in 2000
• Novel devices when scaled bulk CMOS becomes
  inadequate
• Lists devices, description, potential advantages,
  major challenges, and possible insertion node
• Different novel device types
• Non-bulk CMOS are MOS type devices
• Novel devices are electronic devices, but
  beyond MOS type
• Novel storage are novel storage devices
• Novel systems are new systems, requiring novel
  architectures

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Key PIDS Issues for 2001 ITRS

• Memory and logic
• Impact of accelerated scaling
• MOSFET scaling, process, other issues
• Particularly, availability of gate dielectric for
  lt65 nm Lg
• DRAM cell size, equivalent Tox, leakage, etc.
• Circuit, systems issues (with Design TWG)
• Impact of gate leakage on logic, including
  dynamic logic
• Gate resistance
• Static and overall power dissipation
• Meeting device requirements at Low Vdd
• Develop new rows for Flash and FERAM (with FEP
  TWG)
• Expand low power logic requirements (with FEP
  TWG)
• New, extremely low power (handheld, wireless)
  category
• Impact on gate leakage, gate dielectrics

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IRC/Litho. Scaling Proposals for 2001 ITRS
ITRS Roadmap Acceleration Continues...
(Including MPU/ASIC

Physical Gate Length

Proposal
)
500
500
1994
Note MPU/ASIC Physical Bottom Gate Length
350
350
still under discussion.
250
250
(DRAM Half Pitch)
Technology Node
1997
180
180
1998/1999
MPU/ASIC
130
130
2000/2001
Gate Length
Feature Size (nm)
100
100
XX
Technology Node - DRAM Half-Pitch (nm)
Minimum
90
70
XX
70
Feature Size
65

50
XX
50
45
35
XX
35

MPU Gate
1999 ITRS In Resist 2000 ITRS
33
25


XX
25
23
16
.7x per
Year of Production
technology
2001 Renewal Period
node (.5x
REV 1kg_g - 10/20/00
per 2 nodes)
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Key PIDS Issues for 2001 ITRS (cont)

• Analog/RF
• General review of process/integration issues
• Issues with high K coupling, bypass, and other
  capacitors (with Interconnect TWG)
• Need for precision passive elements
• Impact of gate leakage
• SiGe
• Reliability
• Review possible burn-in requirements and SOC
  requirements
• Management of reliability issues with many new
  materials

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Summary

• 2000 update gate length scaling accelerated
  through 2001
• Other, minor updates and changes
• Novel device table added
• 2001 ITRS
• Further acceleration of MPU and DRAM scaling
  proposed
• Difficult issues, especially with gate dielectric
• Many important issues need attention
• Inter-TWG cooperation is vital
• Add FERAM, flash memory, low standby power,
  possibly MRAM

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FOLLOWING ARE BACKUP FOILS
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Issues with Accelerated Scaling, 2001 ITRS

• Proposed by IRC Litho further acceleration in
  MPU scaling compared to 2000 ITRS
• DRAM 0.7X per node (every 3 years)
• Results slightly faster than one year pull in
  from 99 ITRS
• MPU gate length (Lg)
• In photoresist Lg 0.7X DRAM half pitch
• Lg (physical) lt Lg (in photoresist) gt etch bias
• Result two year pull in from 99 ITRS, one year
  from 2000 ITRS
• Issue 1 early onset of process and control
  difficulties, including
• MPU CD error budget, control of etch bias
• DRAM litho, etch, and difficult high K dep.
  (high A/R)
• Very shallow, heavily doped junctions

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IRC/Litho. Scaling Proposals for 2001 ITRS
ITRS Roadmap Acceleration Continues...
(Including MPU/ASIC

Physical Gate Length

Proposal
)
500
500
1994
Note MPU/ASIC Physical Bottom Gate Length
350
350
still under discussion.
250
250
(DRAM Half Pitch)
Technology Node
1997
180
180
1998/1999
MPU/ASIC
130
130
2000/2001
Gate Length
Feature Size (nm)
100
100
XX
Technology Node - DRAM Half-Pitch (nm)
Minimum
90
70
XX
70
Feature Size
65

50
XX
50
45
35
XX
35

MPU Gate
1999 ITRS In Resist 2000 ITRS
33
25


XX
25
23
16
.7x per
Year of Production
technology
2001 Renewal Period
node (.5x
REV 1kg_g - 10/20/00
per 2 nodes)
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Accelerated Scaling Proposals for 2001 ITRS
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Issues with Accelerated Scaling, 2001 ITRS (cont)

• Issue 2 early onset of difficult MOSFETscaling
  issues, including
• High K gate dielectric may be required by
  2003-2004
• Especially problematical for low power technology
• Low contact resistance, low sheet resistance
  silicide
• Channel engineering controlling short channel
  effects
• Control of Vt statistical variation
• Issue 3 early onset of difficult DRAM scaling
  issues, including
• New High K dielectric materials
• Leakage current
• Major re-evaluation of scaling, process, and
  process control issues will be needed

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Tox Scaling and High K Gate Dielectric