332:578 Deep Submicron VLSI Design Lecture 18 DRAM, CAMs, ROMs, and PLAs

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332578 Deep SubmicronVLSI DesignLecture 18
DRAM, CAMs, ROMs, and PLAs

• David Harris and Mike Bushnell
• Harvey Mudd College and Rutgers University
• Spring 2005

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Outline

• DRAM Design
• ROM
• Content-Addressable Memories
• Read-Only Memories
• Programmable Logic Arrays
• Summary

Material from CMOS VLSI Design By Neil E. Weste
and David Harris and VLSI Engineering By Thomas
E. Dillinger
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Memory Categories
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Memory Array Architecture
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RAM Evolution

• Delete a bit line pass transistor to get a
  5-transistor cell (writing is tricky)
• Delete both loads to get a 4-transistor cell

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3 Transistor RAM Evolution

• Cell is now dynamic must be refreshed
• 3 Transistor DRAM store data on gate of storage
  transistor
• Use separate read write control lines
• Add multiple read ports by adding read transistors

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Operation

• Precharge bit line to VDD/2
• When word line rises, bit line shares charge with
  cell
• Causes DV voltage change that can be sensed
• DV voltage is amplified into full 0 or logic 1 on
  bit line
• Read destroys cell contents
• Must write back from amplified bit line into cell
• Make DRAM C small for density

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Cell C Sizing

• Voltage swing equation
• Need large cell C to get acceptable voltage
  swing 30 fF
• Use trench capacitor etched under transistor
  source
• Line with oxide-nitride-oxide dielectric fill
  with poly
• Substrate is other capacitor terminal

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Present-Day DRAM Cell
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Alternate Present-Day DRAM Cell
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Layout for DRAM Cell
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Current DRAM Device

• Problems
• Leakage of stored charge
• Leakage due to stray substrate currents in nearby
  logic
• Use static 6-transistor cell for ASICs easiest
  to design, safest with respect to noise

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SRAM/DRAM Critical Path

• Clock-address delay
• Row address driver time
• Row decode time
• BIT-line sense time
• Setup for a data register
• Column decode time no problem because it has
  the row access time BIT-line sense time for
  operation
• Write faster than read because BIT and BIT are
  actively driven
• Increase speed
• Resize BIT line pullups
• Pipeline row decode signal

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SRAM/DRAM Readout

• Charge Transfer Ratio Cnode
• 
  Cnode n X Cbitline
• DVbitline Charge Transfer Ratio X (Vnode
  Vprecharge)
• Cbitline BIT line C / row
• n rows
• Vprecharge BIT line precharge V
• Vnode DRAM Node storage V
• Use balanced Sense amplifier in the middle of a
  split array
• Equal memory cells on either side

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DRAM Write Cycle

• Write Cycle
• Drop fP
• Raise Word lines
• Raise fL
• Dummy cell voltage should be halfway between bit
  line 0 and 1 voltages

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Read Cycle

• fP 1 and fL 1 BIT lines settle to same
  voltage
• Drop fP fL
• Select word line dummy word line
• Restore BIT line signal to digital value write
  back to the read cell

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Old Open Bit-Line Arch.
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Folded Bit-Line Architecture

• Less noisy must now combine with twisted
  bit-lines

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Folded Bit-Lines
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Lynn-Schediwy Decoder

• 2n input NORs sharing pMOS pullups
• Logic effort of 1.5 per word line (NOR3 has 7/3)

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Row Decoders

• Use domino AND CMOS
• Problem High power consumption
• All row decoders must precharge but only 1
  evaluates to 1
• Benefit 33 faster than static CMOS

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K A B Comparator

• Comparison can be done faster than computing AB
• Because no carry propagation is required
• If you know A and B, you know what carry in to
  each bit must be if K A B
• Need only check adjacent bit pairs
• Verify that previous bit produces required carry
  for the current bit
• Use 1s detector to check that condition is true
  for all N pairs of carries

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Required Carries
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Equations and Circuit
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Uses in SRAM Caches

• Sum-addressed decoder
• For addressing modes where effective address is
  sum of 2 values
• Bias address offset
• In conventional cache SRAM must 1st add 2 values
  and then decode to determine cache word line
• Sum-addressed decoder for N-word memory has 2
  inputs
• A and B
• Has N comparators driving N word lines
• 1st checks if A B 0, 2nd checks if A B 1,
  

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Twisted Bit Line Structure

• For SRAMs to equalize coupling between bit lines

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CAMs

• Extension of ordinary memory (e.g., SRAM)
• Read and write memory as usual
• Also match to see which words contain a key

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CAM
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Content-Addressable Memory

• Use to implement Cache memories and Translation
  Lookaside Buffers for Virtual Memory
• Matching
• Place data to be matched on BIT lines do not
  assert WORD
• Each MATCH line remains high if data matches cell
  contents
• Can use to assert WORD line
• Nor all MATCH lines together to indicate a match

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9T CAM Cell
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10T CAM Cell

• Add four match transistors to 6T SRAM
• 56 x 43 l unit cell

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CAM Cell Operation

• Read and write like ordinary SRAM
• For matching
• Leave wordline low
• Precharge matchlines
• Place key on bitlines
• Matchlines evaluate
• Miss line
• Pseudo-nMOS NOR of match lines
• Goes high if no words match

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Read-Only Memories

• Read-Only Memories are nonvolatile
• Retain their contents when power is removed
• Mask-programmed ROMs use one transistor per bit
• Presence or absence determines 1 or 0
• Use transistor programming in mprocessors to
  minimize dynamic power dissipation

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ROM Example

• 4-word x 6-bit ROM
• Represented with dot diagram
• Dots indicate 1s in ROM

Word 0 010101 Word 1 011001 Word 2 100101 Word
3 101010
Looks like 6 4-input pseudo-nMOS NORs
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Dynamic CMOS ROM

• Word lines forced low while BIT lines are
  precharged
• Avoids DC current flow no DC current usage
• Use same row decoder as for RAM needs smaller
  pitch
• Column decoder simpler than for RAM
• Only READ operations
• Use single-ended sensing
• Mask programming
• Contact programming
• Transistor
• presence/absence
• Implant

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ROM Array Layout

• Unit cell is 12 x 8 l (about 1/10 size of SRAM)

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Row Decoders

• ROM row decoders must pitch-match with ROM
• Only a single track per word!

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Complete ROM Layout
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PROMs and EPROMs

• Programmable ROMs
• Build array with transistors at every site
• Burn out fuses to disable unwanted transistors
• Electrically Programmable ROMs
• Use floating gate to turn off unwanted
  transistors
• EPROM, EEPROM, Flash

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Building Logic with ROMs

• Use ROM as lookup table containing truth table
• n inputs, k outputs requires __ words x __ bits
• Changing function is easy reprogram ROM
• Finite State Machine
• n inputs, k outputs, s bits of state
• Build with ________ bit ROM and ____ bit reg

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Building Logic with ROMs

• Use ROM as lookup table containing truth table
• n inputs, k outputs requires 2n words x k bits
• Changing function is easy reprogram ROM
• Finite State Machine
• n inputs, k outputs, s bits of state
• Build with 2ns x (ks) bit ROM and (ks) bit reg

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Example RoboAnt

• Lets build an Ant
• Sensors Antennae
• (L,R) 1 when in contact
• Actuators Legs
• Forward step F
• Ten degree turns TL, TR
• Goal make our ant smart enough to
• get out of a maze
• Strategy keep right antenna on wall
• (RoboAnt adapted from MIT 6.004 2002
  OpenCourseWare by Ward and Terman)

L
R
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Lost in space

• Action go forward until we hit something
• Initial state

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Bonk!!!

• Action turn left (rotate counterclockwise)
• Until we dont touch anymore

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A little to the right

• Action step forward and turn right a little
• Looking for wall

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Then a little to the right

• Action step and turn left a little, until not
  touching

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Whoops a corner!

• Action step and turn right until hitting next
  wall

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Simplification

• Merge equivalent states where possible

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State Transition Table
Lost
RCCW
Wall1
Wall2
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ROM Implementation

• 16-word x 5 bit ROM

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ROM Implementation

• 16-word x 5 bit ROM

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PLAs

• A Programmable Logic Array performs any function
  in sum-of-products form.
• Literals inputs complements
• Products / Minterms AND of literals
• Outputs OR of Minterms
• Example Full Adder

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NOR-NOR PLAs

• ANDs and ORs are not very efficient in CMOS
• Dynamic or Pseudo-nMOS NORs are very efficient
• Use DeMorgans Law to convert to all NORs

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PLA Schematic Layout
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PLAs vs. ROMs

• The OR plane of the PLA is like the ROM array
• The AND plane of the PLA is like the ROM decoder
• PLAs are more flexible than ROMs
• No need to have 2n rows for n inputs
• Only generate the minterms that are needed
• Take advantage of logic simplification

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Example RoboAnt PLA

• Convert state transition table to logic equations

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RoboAnt Dot Diagram
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RoboAnt Dot Diagram
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DRAM Evolution
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Summary

• DRAM Design
• Content-Addressable Memories
• Read-Only Memories
• Programmable Logic Arrays