Some Data Rate Issues in the L1 Trigger System

1
Some Data Rate Issues in the L1 Trigger System

• July 2004

2
Outline

• Capacities of data flow at the connection ports.
• Relative data rate evolution in each stage.

3
L1 Block Diagram
Pixel Data
Time Stamp Ordering
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
Raw Data to L1B
Cluster Processing
Triplets to L1B
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
Data Sharing
ST
L1B
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
Segment Finding
L1B Servers
L1 Switch
Event Building
Tracks Vertices to L1B
BM
BM
BM
BM
BM
BM
BM
BM
L1B
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
Track Vertex Processing
L1B Servers
GL1 Node
Trigger primitives to GL1
4
Gang Things Together Reroute Cables
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
TSO
Events are built during TSO PP processing.
L1B for raw data, triplets etc.
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
Triple links are not needed.
ST
L1B
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
ST
L1B Servers
L1 Switch
BM
BM
BM
BM
BM
BM
BM
BM
L1B
L1 Switch is gone, its functions are absorbed in
TSO PP stages.
CPU
CPU
CPU
CPU
CPU
CPU
CPU
CPU
L1B Servers
GL1 Node
5
System Interconnection (1 Hwy)
Time Stamp Ordering Module
Segment Tracker L1B Module
L1B Server PC
Pixel Pre-processor Module
Buffer Manager Module
Worker Farm Node
6
A possible GL1 Interconnection
(3) The same BM module is used as GL1 interface.
GL1 Node
ST/L1B
(2) The TSO modules can be used as concentrators.
(1) GL1 are sent out by the Worker Nodes.
Farm Nodes
7
Throughput Capacities
8
Relative Data Volume Evolution in Different Stages

• When the data are repackaged (such as in PDCB),
  data rate may be reduced.
• When the data are reordered (such as in Time
  Stamp Ordering Module), data rate may be reduced.
• When the data are duplicated (such as in Pixel
  Pre-processor Module), data rate will increase.

9
Input Output of PDCB
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
b20
b19
b18
b17
b16
b23
b22
b21
Hit24
Row
Column
BCO(70)
ADC
1
DCC et al
12.3 Ghits/s x 24 b/hit 0.3 Tbps (total), 37.5
Gbps/hwy
Doc 3233
Doc 2621
12.3 Ghits/s /(2.5 hits/group)x 48 b/group 236
Gbps (total), 29.5 Gbps/hwy
10
Idling, an Important Operation
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
DW0
Row
Column
Module
DW1
ADC0
BCO(113)
Chip
Optional Continue Word
Hits
0
0
ADC1
ADC2
ADC3
BCO(20)
11
Output of Time Stamp Ordering Module
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
Hits 12.3 Ghits/s /(2.5 hits/group)x 32 b/group
157 Gbps (total), 19.7 Gbps/hwy
12
Output of Pixel Pre-processor Module
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
Raw Hits 12.3 Ghits/s /(2.5 hits/cluster)x 32
b/cluster 157 Gbps (total), 19.7 Gbps/hwy
XY 12.3 Ghits/s /(2.5 hits/group)x (3216)b/(2
groups) 118 Gbps (total), 14.7 Gbps/hwy
13
Data Rates
14
Conclusion

• We have large safety factors.

15
I/O of Time Stamp Ordering Module
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
DW0
Row
Column
Chip
DW1
ADC0
BCO(113)
Module
Optional Continue Word
Hits
0
0
ADC1
ADC2
ADC3
BCO(20)
Idle Words
1
1
1
X
0
Status etc.
1
1
1
X
0
Status etc.
00
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
Station
BCO(70)
0
0
Header Long Word
BCO(237)
Row
Column
Chip
Hits Long Word
ADC0
Module
Hits
ADC1
ADC2
Idle Long Words
16
I/O of Time Stamp Ordering Module
b04
b03
b02
b01
b00
b09
b08
b07
b06
b05
b14
b13
b12
b11
b10
b15
DW0
Row
Column
Chip
DW1
ADC0
BCO(113)
Module
Optional Continue Word
Hits
0
0
ADC1
ADC2
ADC3
BCO(20)
Hits 12.3 Ghits/s /(2.5 hits/group)x 32 b/group
157 Gbps (total), 19.7 Gbps/hwy
Headers (1/hwy) 7.6 MBOC/s x (1/8hwy) x
32b/BCO/port x 480 ports 14.6 Gbps/hwy