Building smart, adaptive and efficient systems for networked applications

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Networked Embedded System-on-Chip

• Building smart, adaptive and efficient systems
  for networked applications
• Rajesh K. Gupta
• Center for Embedded Computer Systems
• University of California, Irvine.
• http//www.ics.uci.edu/rgupta

2
Outline

• Networked embedded systems
• Design technology challenges in NES
• Data management for NES
• Using NES in Smart, Adaptive Spaces

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Semiconductor System Chips

• Two trends
• increasing use of embedded intelligence
• networking of embedded intelligence
• In ten years
• the big e.g., terabit optical core, gigabit
  wireless, ...
• the small e.g., pervasive self-powered sensor
  motes
• the cheap e.g., one-cent radios
• short-range (10-100m), low power (10nJ/bit), low
  bit rate (1-100kbps)
• The consequence
• smart spaces, intelligent interfaces, ad hoc
  networks

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The Consequence Pervasive Embedded Intelligence
Closed loop control
In-body
MEMS Sensors
Neuro-stimulators
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Challenges and Constraints

• Semiconductor technology scaling gives rise to
  three key challenges
• Challenge of scalability
• the need to extend communications and processing
  to large data, over heterogenous channels
• Challenge of adaptation
• the need to reuse and retarget both hardware and
  software
• Challenge of integration
• the need to more optimally exploit heterogenous
  component technologies with respect to cost,
  performance, energy tradeoffs
• Fundamental technology constraints as well
• energy (limitations of batteries, sensors)
• bandwidth (limited speed of semiconductor
  devices)
• non-scalability of analog circuits
• scaling of on- and off-chip interconnects

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The Grand Challenge

• How do we enable systems-on-chip realizations
  of networked embedded applications that take full
  advantage of design infrastructure, interconnects
  and devices in gigascale silicon?

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Mission

• Enable silicon technology to realize goals of
  SOC-based system designers
• by providing cost, performance, power, and
  robustness driven system optimizations that span
  traditional divisions among circuits, systems and
  devices
• by providing fundamental new circuits and
  software configurations and
• by providing new levels of integrated
  intelligence, computation and adaptation.

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Question How Do We Design Such SOC?

• Next set of slides outline SOC Design Technology
  Challenges and Approaches

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NES Compositional View

• Integrated heterogenous systems
• hardware/software
• mixed analog/digital (RF/BB)
• bigger but badder chips
• Examples
• single-chip HDTV, single-chip GSM

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NES Functional View

• On-chip application computing
• On-chip communication and networking
• Indeed, complete integration of all layers of a
  networked node on a single chip
• physical ? transceiver, modem
• link/MAC ? packet scheduling
• routing ? routing protocols
• transport ? TCP
• application ? adaptive buffering
• IC designer is also a networked system designer.

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Systems Engineering for SOCs

• Example Problem How to achieve high throughput
  in a SOC for wireless applications?
• Can select a modem sub-system
• that packs more bits/Hz, but it will tolerate
  less noise and be less robust so that link
  throughput may not improve
• Can increase transmit power in RF subsystem
• to improve robustness but this increases energy
  cost, reduces network capacity, and requires more
  expensive analog circuits (power amps)
• Can reduce bits/frame
• to tolerate higher bit error rates (BER) and
  provide more robustness, but this may increase
  overhead and queuing delays
• Can increase precision in digital modem
• to reduce noise, but this leads to wider on-chip
  busses and more power consumption
• The design technology must support right
  sub-system option and parametric determination.

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SOC Design Challenges

• Circuits with minimal analog processing
• Maximize digital computation
• Reuse communication, multimedia modules
• Energy efficient software
• Flexible, low power protocol processing

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Traditional Design Process

• Paper, pencil, calculator
• Many board turns (cut and try)
• Long design cycles

Courtesy HP
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System-level Design

• Goal is to quickly and accurately analyze system
  performance
• Top-level system brainstorming
• Quick analysis of circuit interactions
• Budget analysis to allocate circuit
  specifications
• Design partitioning

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Building SOC Devices

• A Case Study from MORPHOSYS

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Smart, Adaptive, Usable Silicon Devices

• System-Chips that
• consume less power reduce the time between
  recharge
• obtain high performance provide the power of PC
  in a small and low cost design
• A combination of software tools and hardware
  techniques to achieve this goal
• Smart appliances do not need a PC, but fast, low
  cost and low power chips
• AMRM and MORPHOSYS System-Chips
• adapt system architecture to application needs
• AMRM provides adaptive memory architectures for
  SOCs
• MORPHOSYS is an example of an SOC that uses a
  processor core along with a reconfigurable logic
  array to speed up media-processing applications.

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MorphoSys chip
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Voice/Data/Video Compression

• Fax machine example
• for sending a fax of one 8.5 X 11 inch page,
  scanned at 400 dpi, data 7.5 Mbits
• transmission requires 2 minutes (56 kbps modem)
• only 6 seconds with compression (modern fax
  machines transmit 10 pages per minute)
• Video-based CD-ROM
• full motion video has 20.7 Mbytes/s (30 frames
  per second, with 720 by 480 resolution)
• without compression, only 31 seconds of video
  storage in a CD-ROM
• store 74 minutes with compression (VHS grade
  quality)

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Data Rate
Application
Uncompressed
Compressed
Voice TX
64
kbps
2 - 4
kbps
8
ksamples/s, 8 bits/sample
Slow-motion video
5.07
Mbps
8 - 16
kbps
Frame 176x120, 24 bits/pixel
Audio Conference
128
kbps
6 - 64
kbps
8
ksamples/s, 16 bits/sample
Digital audio (stereo)
1.5
Mbps
128 - 768
kbps
44.1
ksamples/s, 16 bits/sample
Video file transfer
30.41
Mbps
384
kbps
framesize 352 X 240, 24 bits/pixel
digital video on CD-ROM (30 fps)
60.83
Mbps
1.5 - 4
Mbps
framesize 352 X 240, 24 bits/pixel
Broadcast (NTSC) video (30 fps)
248.83
Mbps
3 - 8
Mbps
framesize 720 X 480, 24 bits/pixel
HDTV (60 fps)
1.33
Gbps
20
Mbps
framesize 1280 X 720, 24 bits/pixel
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Motion estimation
2100
2100
Slower
1800
1500
1159
1200
Cycles
900
631
581
540
600
300
Faster
0
MorphoSys
ASIC HL92
ASIC
ASIC
TMS320C64X
M1
NBLL94
YSW89
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Encryption
153
150
125
100
Cycles/ciphertext block
75
50
16
25
4.5
0
MorphoSys
Pentium II PC
HiPCrypto
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Managing Data for SOC-enabled Devices

• How to do quality-aware data management that
  applications using these devices will need.

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Quality-Aware Data Management

• Goal
• build scalable database support for dynamic
  multi-resolution, multi-spectral data
• Approach
• Multi-Resolution Aggregate Tree (MRA-tree), a
  technique that provides progressively improving
  answers at a guaranteed quality level for
  aggregate queries

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Build Device Databases

• Large number of smart devices
• produce large volume of information at a high
  rate
• yet limited by communication and energy
  constraints.

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Quality-Aware Data Management

• Data is imprecise
• Queries have quality requirements
• The Goal Build a database system that
• is aware of multiple levels of imprecision in
  data
• can answer queries at multiple levels of quality
• makes optimum use of the system resources.
• Applications that can directly use QADM
• Flying through a large-scale, high quality
  virtual environment
• Monitoring and Querying a weather Database
• Using your cars computer to get accurate
  real-time traffic updates
• Interacting with millions of other people in a
  real immersive multi-player game.

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NES SOC Applications

• Possibilities
• Instrumented wide-area spaces
• Living laboratory (personal area spaces)
• Internet end-points
• In-body, In-cell, In-vitro (I3) spaces

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Wireless Sensor Network Node
SmartSensorNode
T1
Event
Internet
SmartSensorNode
Gateway
T2
SmartSensorNode
T3
SmartSensorNode
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Wireless Sensor Node SOCs
Sensor Node Control Query Server
Beamformation
Fuse features with neighbors
Query/corroborate with neighbors
cooperative
Transport
Fuse multiple on-board sensors
Routing
autonomous
Process single sensor
Link/MAC
Continuous sample, HW filter, threshold compare
Radio Modem
Sensor Signal Processing Services
Networking Services
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NES SOC Applications

• Possibilities
• Instrumented wide-area spaces
• Living laboratory (personal area spaces)
• Internet end-points
• In-body, In-cell, In-vitro (I3) spaces

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Smart HomeA Proxy for Smart Adaptive Interfaces

• Often a playroom full of appliances and sensors
• Brings networking and automation into homes with
  appliances that
• connect to the web
• communicate with each other
• interact with us
• make decisions based on prearranged goals
• Visions
• SH technology issues

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Current Vision

• Early versions of home networking technology
• Often PC-centric view of the home-space
• Intelligent and networked appliances
• e.g., Sunbeam HTL appliances and others
• coffeemaker, blanket controller, smoke alarm,
  mixmaster
• One touch control of home functions for cases
  such as
• arriving homem bedtime, being away from home,
  etc.
• Broadband telecommunications center
• Focus to monitor inhabitants and evaluate
  behavior
• Uses sensors to monitor touch, motion, and sound
• Smart floors and motion detectors enhance
  interaction

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Going Forward

• Smart and adaptive personal spaces that
  effectively exploit
• smart art (change based on the mood)
• smart music, lighting
• telepresence
• tracking and biometrics
• self repair electronic diagnosis, smart material

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Telepresence

• Integrates video, voice and graphics

• Requirements
• - high bandwith
• - graphics processors

NTT's Cyber Campus
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The Virtual Library
Bibliotheca Alexandrina
01010100010010010
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Education

• Improving
• your knowledge
• from home
• Sneaking into
• your kids class

Virtual Chemist, created by SENSE8 Univ. of
Michigan
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Leisure and travel

• Plan your
• vacations before
• you go
• Get a taste of
• new experiences
• with no risk
• Play games in
• collaborative
• environments

Virtual Hanglider, Created by Evans Sutherland
and SENSE8
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Shopping
See, touch and smell what you are buying then
get it delivered to your home!
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Proposed Smart Home At Irvine

• A proxy for smart adaptive spaces
• not only sensor rich but intelligently navigated
  (both virtually as well as physically)
• Possible Partners
• Center for Pervasive Communications, UCI
• Center for Embedded Computer Systems, UCI
• The Irvine Company
• Schools of Engineering, Social Sciences, Arts,
  etc.
• Pacific Bell
• Include the missing piece
• automobiles
• virtual reality
• architecture

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Technology Exploration Areas

• Mobile code
• (small, portable, composable (as components), JIT
  compiled for power, memory)
• Compiler techniques for mobile nodes
• QoS modeling and analysis for SOC
• across app/network/phy layers
• Efficient middleware
• to enable IP composability and SOC insertion
• Network-to-network models
• of SOCs
• higher-level system usability/reliability/security
  models
• (including user models)

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A Partial List of SOC Innovations To Be Pursued

• A wireless neural transceiver using
  single-channel neural signal recording.
• Cross-layer (communication and computation)
  global optimization strategies that address
  functional diversity of IPs.
• New embedded processor architectures in which all
  components are tuned to application needs, i.e.,
  data paths, memory architectures, architecture
  and ISA.
• Low-voltage circuit and system architectures for
  high performance operation from very low voltage
  (lt 1v).
• Communication transceivers that fully exploit the
  powerful mix of analog and digital on the same
  CMOS chip for higher performance at lower power.
• Systematic methodologies for analog and
  mixed-signal reuse.