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Ulrich Abelein, Mathias Born, Markus Schindler,

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... of the vertical IMOS (above) and SIMS profile of ... 2 -1. 0. 1. Energy in eV. 1010. 1020. 1030. Ionisation rate in pairs / (cm3 s) 0. 80. Distance in nm ... – PowerPoint PPT presentation

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Title: Ulrich Abelein, Mathias Born, Markus Schindler,


1
Doping Profile Dependence of the Vertical Impact
Ionization MOSFETs (I-MOS) Performance
  • Nano and Giga Challenges in Electronics and
    Photonics
  • NGC 2007
  • Phoenix, Arizona, USA
  • 16 March 2007

2
Overview
  • Motivation
  • Vertical Impact Ionisation MOSFET (IMOS)
  • Device Concept
  • Influence of Doping Profiles
  • Electrical Characterization
  • Summary and Outlook

3
Motivation
  • Conventional MOSFET
  • Subthreshold slope S dVG/d(logID) is diffusion
    limited.
  • ? min S kT/q ln10 60 mV/dec _at_ 300 K
  • Minimum static leakage current ILEAK
  • ILEAK ID(VT) 10-VT/S
  • Shrinking the feature size according to Moores
    Law makes a reduction of VT necessary.
  • ? ILEAK ?
  • Solution ? Reducing S below the kT/q limit!
  • ?
  • Achievable by gate controlled impact ionisation
  • ? Impact Ionisation MOSFET (IMOS)

4
Device Concept Device Structure
Drain contact
p delta layer
Gate oxide (4.5 nm)
Gate oxide (4.5 nm)
Spacer
Spacer
n Si drain
Gate contact
n Poly
i- Si
i- Si
n Poly
n Si source
Source contact
Schematic drawing of the vertical IMOS (above)
and SIMS profile of the mesa layer stack (left
hand side)
5
Device Concept Simulation Results
? p delta barrier lowered by gate field ? High
field between p delta layer and drain causes
impact ionisation
Drain contact
Spacer
Spacer
p delta layer
n Si drain
Gate oxide
Energy in eV
-1
1
-2
0
i- Si
Gate contact
Drain
80
i- Si
n Poly
Distance in nm
VGSVDS0 V VGS0 V VDS2 V VGS VDS2 V
n Si source
0
Source
1010
1020
1030
Ionisation rate in pairs / (cm3?s)
Source contact
Simulations of the electric field and the
ionisation rate in the channel region
6
Device Concept Operating Modes
  • VDS lt 1.25 V
  • ? Conventional MOSFET mode
  • 2.2 V gt VDS gt 1.25 V
  • ? Impact Ionization Mode
  • ? Holes generated by impact ionization charge
    the body.
  • Dynamic lowering of VT!
  • VDS gt 2.2 V
  • ? Bipolar Mode
  • ? Parasitic bipolar transistor contributes to
    ID

W 2µm
7
Device Concept Operating Modes
  • VDS lt 1.25 V
  • ? Conventional MOSFET mode
  • VDS gt 1.25 V
  • ? Beginning of significant impact ionziation
  • ? Holes generated by impact ionization charge
    the body
  • ? Dynamic lowering of VT
  • ? S is reduced below kT/q

W 2 µm
8
Influence of Doping Profiles
  • Unintentional changes in doping profiles due to
    diffusion!
  • ? p delta layer doping diffuses into intrinsic
    zones!
  • Diffusion ? ? Sharper delta layer, larger
    barrier, higher eelctric fields!
  • ? Impact Ionization rates ? (at const. VDS)
  • ? Lower S due to increased body charge for low
    VDS
  • Diffusion ? ? Lower barrier
  • ? Switch on voltage of parasitic bipolar
    transistor ?
  • ? Extremley low S due to current amplification
  • ? Hysteresis in input characteristics

9
Experimental Results Doping Profiles
  • Using 750 C and
  • 800 C gate oxide process
  • Decreasing of boron diffusion for 750 C
  • ? Maximum doping level increased by a factor
    of 3
  • ? Larger barrier!

10
Electrical Characerization Output
Characteristics
  • Low thermal budget sample
  • ? Impact ionization mode begins at lower
    voltage
  • ? Later transistion to bipolar mode
  • ? VDS 2.25 V
  • LT sample in Impact Ioniziation mode
  • HT sample in bipolar mode

W 2 µm
11
Electrical Characerization Input Characteristics
VDS 2.25 V ? LT sample in Impact Ioniziation
mode ? S 4 mV/dec ? No hysteresis!
W 2 µm
12
Electrical Characerization Input Characteristics
VDS 2.25 V ? HT sample in bipolar mode ? S
1.06 mV/dec! ? Hysteresis visible ? Gate
controlled switch-off possible!
W 2µm
13
Summary and Outlook
  • Summary
  • Influence of boron diffusion on device
    performance was shown
  • Subthreshold slope of 1.06 mV/dec was shown
  • Devcie can be optimized to needs of application
  • Very low subthreshold slope with measurable
    hysteresis
  • Low subthreshold slope without any hystersis
  • Outlook
  • Realization of the p-channel device
  • Shrinking device dimensions and reducing supply
    voltages
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