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Synthesis of Asynchronous systems: Issues and approaches

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Dual rail. Two wires with L(low) and H (high) per bit 'LL' = 'spacer', 'LH' = '0', 'HL' = '1' ... Technology mapping is more difficult, verification is easy ... – PowerPoint PPT presentation

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Title: Synthesis of Asynchronous systems: Issues and approaches


1
Synthesis of Asynchronous systemsIssues and
approaches
  • - Deepak Baranwal (2003EEY0011)

2
Outline
  • Basic concepts on asynchronous design
  • Asynchronous design styles
  • Control specification and implementation
  • Logic synthesis from concurrent specifications
  • Issues

3
Synchronous circuit
Implicit (global) synchronization between
blocks Clock period gt Max Delay (CL R)
4
Asynchronous circuit
Ack
R
R
R
R
CL
CL
CL
Req
Explicit (local) synchronization Req / Ack
handshakes
5
Globally Async Locally Sync (GALS)
Asynchronous World
Clocked Domain
Req3
Req1
R
R
CL
Ack3
Ack1
Local CLK
Req4
Req2
Ack4
Ack2
Async-to-sync Wrapper
6
Key Design Differences
  • Synchronous logic design
  • proceeds without taking timing correctness(hazard
    s, signal acking etc.) into account
  • Combinational logic and memory latches(registers)
    are built separately
  • Static timing analysis of CL is sufficient
    todetermine the Max Delay (clock period)
  • Fixed setup and hold conditions for latches

7
Key Design Differences
  • Asynchronous logic design
  • Must ensure hazardfreedom, signal acking,local
    timing constraints
  • Combinational logic and memory latches
    (registers) are often mixed in complex gates
  • Dynamic timing analysis of logic is needed to
    determine relative delays between paths
  • To avoid complex issues, circuits may be builtas
    Delay-insensitive and/or Speed-independent

8
Synchronous communication
1
1
0
0
1
0
  • Clock edges determine the time instants where
    data must be sampled
  • Data wires may glitch between clock
    edges(setup/hold times must be satisfied)
  • Data are transmitted at a fixed rate(clock
    frequency)

9
Dual rail
1
1
1
0
0
0
  • Two wires with L(low) and H (high) per bit
  • LL spacer, LH 0, HL 1
  • nbit data communication requires 2n wires
  • Each bit is self-timed
  • Other delay-insensitive codes exist (e.g.
    k-of-n)and eventbased signalling (choice
    criteria pin and power efficiency)

10
Bundled data
1
1
0
0
1
0
  • Validity signal
  • Similar to an aperiodic local clock
  • nbit data communication requires n1 wires
  • Data wires may glitch when no valid
  • Signaling protocols
  • level sensitive (latch)
  • transition sensitive (register) 2phase /
    4phase

11
Example memory read cycle
Valid address
Address
A
A
Valid data
Data
D
D
  • Transition signaling, 4-phase

12
Asynchronous modules
DATA PATH
Data IN
Data OUT
start
done
req in
req out
CONTROL
ack in
ack out
  • Signaling protocol
  • reqin start computation done reqout
    ackout ackinreqin- start- reset
    done- reqout- ackout- ackin-(more
    concurrency is also possible)

13
Elements for Asynchronous Design
Dual-rail logic
C
done
A B Z 0 0 0 0 1 Z 1
0 Z 1 1 1


C-element
Dual-rail AND gate
Completion detection circuit
14
Micropipelines (Sutherland 89)
Aout
Ain
C
L
L
L
L
logic
logic
logic
Rin
Rout
15
Data-path / Control
L
L
L
L
logic
logic
logic
Rin
Rout
CONTROL
Ain
Aout
16
Control specification
A
A
B
B
A
A input B output
B
17
A simple filter specification
IN
Rin
Ain
y 0 loop x READ (IN) WRITE (OUT,
(xy)/2) y x end loop
filter
Aout
Rout
OUT
18
A simple filter block diagram
  • x and y are level-sensitive latches (transparent
    when R1)
  • is a bundled-data adder (matched delay between
    Ra and Aa)
  • Rin indicates the validity of IN
  • After Ain the environment is allowed to change
    IN
  • (Rout,Aout) control a level-sensitive latch at
    the output

19
A simple filter control spec.
20
Delay models for async. circuits
  • Bounded delays (BD) realistic for gates and
    wires.
  • Technology mapping is easy, verification is
    difficult
  • Speed independent (SI) Unbounded (pessimistic)
    delays for gates and negligible (optimistic)
    delays for wires.
  • Technology mapping is more difficult,
    verification is easy
  • Delay insensitive (DI) Unbounded (pessimistic)
    delays for gates and wires.
  • DI class (built out of basic gates) is almost
    empty
  • Quasi-delay insensitive (QDI) Delay insensitive
    except for critical wire forks (isochronic
    forks).
  • In practice it is the same as speed independent

BD
SI ? QDI
21
Channel-Based Design
Asynchronous channel
clock
Synchronous System
Asynchronous System
  • Synchronization and communication between blocks
  • implemented with handshaking using asynchronous
    channels by sending/receiving data tokens

22
Design flow for AHLS
Algorithm
Compilation
Compilation
DFG
Scheduling/ Allocation
Async. Scheduling model
Binding/ Reg. allocation
Async. Architecture model
STG spec
Architecture
CIRCUIT
23
Scheduling
  • From a library of components including
    their average computation delays, for a DFG and a
    cost constraint, define a partial order if the
    different operation execution in order to
    minimize the average delay estimation of the
    global system represented by DFG.

X1
X3
X5
Mult2
2
5
Mult1
1
3
6
7
X2
4
Adder
4
6
7
0
40
100
50
80
Asynchronous scheduling T 100 ns Tadder 40ns
Synchronous scheduling T 4 cycles (
4x40160ns) Tmult 40ns
24
Binding
  • Binding consists of allocating each
    operation to an operator. Asynchronous binding
    uses a similar approach as for synchronous
    binding but it also gives the possibility to use
    dynamic binding.

Selection
Input
Selection
Input
Distribution
Contol_2
Op 2
Contol_1
Contol_2
Op 1
Op 2
Selection
Distribution
Distribution
Static binding
Output
Dynamic binding
Output
25
Design flow for synthesis
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
26
Specification
x
x
y
y
z
z
x-
z
x
y
z-
y-
Signal Transition Graph (STG)
27
Token flow
28
State graph
29
Next-state functions
30
Gate netlist
x
y
z
31
Design flow
Specification(STG)
Reachability analysis
State Graph
State encoding
SG withCSC
Boolean minimization
Next-state functions
Logic decomposition
Decomposed functions
Technology mapping
Gate netlist
32
Speed independence
  • Delay model
  • Unbounded gate / environment delays
  • Certain wire delays shorter than certain paths in
    the circuit
  • Conditions for implementability
  • Consistency (SG is strongly connected)
  • Complete State Coding (Unique states in SG)
  • Persistency (Only firing can disable enabled
    transition)

33
Implementability conditions
  • Consistency CSC persistency
  • There exists a speed-independent circuit that
    implements the behavior of the STG(under the
    assumption that any Boolean function can be
    implemented with one complex gate)

34
(No Transcript)
35
ER(d)
ER(d-)
36
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
Complex gate
37
Implementation with C elements
? S ? z ? S- ? R ? z- ? R- ?
  • S (set) and R (reset) must be mutually exclusive
  • S must cover ER(z) and must not intersect
    ER(z-) ? QR(z-)
  • R must cover ER(z-) and must not intersect
    ER(z) ? QR(z)

38
ab
cd
00
01
11
10
0
0
0
0
00
1
0
01
1
1
1
1
11
1
10
S
d
C
R
39
Speed-independent implementations
  • Implementability conditions
  • Consistency
  • Complete state coding
  • Persistency
  • Circuit architectures
  • Complex (hazard-free) gates
  • C elements with monotonic covers
  • ...

40
Issues
  • Modelling language for asynchronous design
  • LARD (language for async research development)
    Manchester Univ.
  • BALSA
  • VHDL-200x (IEEE) etc..
  • Synthesis automation
  • Petrify (a tool for synthesis of Petri Nets)
  • Problem for state-explosion (depends on number of
    signals)
  • Verification

41
Conclusion
  • Asynchronous design provides delay-independent
    circuits.
  • Synthesis from STGs can be fully automated.
  • Great reduction in power
  • No affect in functionality

42
References
  • High level Synthesis of Asyn. Systems
    Scheduling and Synchronization Badia et al,.
  • Behavioral Synthesis of Asynchronous systems A
    methodology Dedou et al.
  • Automated Synthesis of Asyn. Circuits from High
    level specifications Meng et al.
  • Petrify a tool for manipulating concurrent
    specifications and synthesis of asynchronous
    controllers Cortadella et al. IEEE trans on
    information and systems
  • Amulet3i an Asynchronous Sytsem-on-Chip
    Furber et al.
  • Special Reference Tutorial on Asynchronous
    design methodologies Cortadella et al., VLSI
    Conf04 (http//www.lsi.upc.es/jordicf/publicatio
    ns/tutorials.html)
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