The Impact of Variability on the Reliability of Long onchip Interconnect in the Presence of Crosstal

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The Impact of Variability on the Reliability of
Long on-chip Interconnect in the Presence of
Crosstalk
Basel Halak, Santosh Shedabale, Hiran
Ramakrishnan, Alex Yakovlev, Gordon
Russell Newcastle University UK
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Outline

• Structure and fabrications of Modern Interconnect
• Why are two nominally identical wires different ?
• Impact of variability on Wire Delay and Crosstalk
  Glitches
• What are the Failure Mechanism in
  Capacitance-Dominated links ?
• Does Variability make things worse ?
• Conclusions

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Interconnect Stack in Modern Technologies
Source ITRS 2007
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How to Build Multilayer's Interconnect Structure
1. Start with the previous interlayer dielectric
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How to Build Multilayer's Interconnect Structure
2. Add an etch stop' layer
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How to Build Multilayer's Interconnect Structure
3. Add a new layer of intra-layer dielectric
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How to Build Multilayer's Interconnect Structure
4. Etch spots in the dielectric for wires
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How to Build Multilayer's Interconnect Structure
5. Deposit the barrier metal
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How to Build Multilayer's Interconnect Structure
6. Deposit the metal
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How to Build Multilayer's Interconnect Structure
7. Grind it flat
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How to Build Multilayer's Interconnect Structure
8. Add a dielectric cap/via etch stop
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How to Build Multilayer's Interconnect Structure
9. Add more inter-layer insulator
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How to Build Multilayer's Interconnect Structure
10. Add another etch stop
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How to Build Multilayer's Interconnect Structure
11. Cut holes in dielectric for the vias
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How to Build Multilayer's Interconnect Structure
12. Cut holes in each stop layer for the vias
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How to Build Multilayer's Interconnect Structure
13. Deposit via metal
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Interconnect Stack in Modern Technologies
14. Repeat the process for more layers
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Variability Sources

• Fabrication Process
• Lithography exact size and shape depend on
  environment
• Etching also depends on environment
• Thickness of metal depends on CMP environment
• Deposition and polishing steps depend on chip
  location on the wafer
• Alignment between layers can affect vias

• Environmental Factors
• power supply and temperature
• Other Factors
• an example of a statistical variation that
  results in deterministic uncertainty CMP
  etching as function of location on a wafer

Source (An Overview of On-chip Interconnect
Variation Lou Scheffer , SLIP 2006 )
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Variability Impact on wire electric parameters
Normalized wire capacitance distribution (C)
Normalized metal resistance across manufacturing
lines (R)
Source Statistical Analysis and Optimization in
the Presence of Gate and Interconnect Delay
Variations Chandu Visweswariah ,IBM,SLIP 2006
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Motivations

• In DSM regime, due to process scaling, the
  contribution of interconnect delay has become
  significant
• Wire delay and coupling effects play a
  significant role in determining ultimate
  performance
• not easy to predict which is the worst corner

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This work
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Wire Model
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Variations
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Delay Sensitivity to Variability Sources
Un-Buffered Line (L10mm, K1)
Uniformly Buffered Line (L10mm,K4)
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Crosstalk Glitches Sensitivity to Variability
Sources
Un-Buffered Line (L10mm, K1)
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The Impact of Switching Activity
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Delay Sensitivity to Variability Sources
Un-Buffered Line (L10mm, K1)
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This work
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Failure Mechanism in Capacitive Coupled Links

• Timing Failure This undesired effects occurs
  when the timing of a stage becomes uncertain due
  to coupling from the switching activity of
  neighboring stages, which results in a change in
  the total capacitance of the wire, hence dynamic
  delay.
• Functional Failure which is caused by static
  noise, induced on a quiet victim net due to
  switching of neighboring aggressors.

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Interconnect States
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BER Analysis
Timing Failure
PE (Dwire gtTclk - Tsetup)
PE -0.5- Q
µ? µD µTsetup µTclk s2? s2D
s2Tsetup s2Tclk
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BER Analysis
Functional Failure
PE Pr (Amp gt Vth)
PE -0.5- Q
µ ? µAmp µVth s 2? s 2Amp s2 Vth
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BER Analysis
BER
P is the Error Rate in each state O is the
probability of Occurrence of each state
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This work
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Variability Good or Bad ?
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How to combat variability ?
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How to combat variability ?
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Conclusions

• Novel bit error rate estimation method
• Mathematical expressions - quick tool to compare
  different design approaches.
• BER model developed for self-timed interconnect
  links
• Future directions - quantifying the variability
  impact on other system metrics