Design of Self_Biasing PLL Architecture and Circuit

1
Design of Self_Biasing PLL Architecture and
Circuit

• PeiQing Zhu
• Southern Methodist University
• 08-29-2005

2
PLL Architecture
3
Introduction of the PLL

• PLL is one of the most key components in the Link
  Of Chip(LOC).The PLL will affect the whole system
  performance. So there exists some standard
  requirements such as OC-48,OC-192.
• Function PLL and MUX converse the parallel data
  into series data and drive the Amp to transmit
  the series data in the transmitter terminal .

4
Block Diagram of Fiber Optic Transceiver System
5
Purpose of First Version PLL

• Verification of the PLL basic functionality.
• Mainly testing the basic PLL parameters such
  as the lock time, jitter performance.
• Compare the performance before and after the
  radiation.
• PLL performance mainly jitter, lock range,
  locking time and stability etc.

6
PLL Architecture Single Loop, Full rate,
Integrate_PLL
VCO output3.12GHz
input signal clock 156MHz
up
PFD
Charge_ Pump loop filter
VCO Biasing
Vcontr
dn
input signal dclock
VCO
Divided_by_20
VCO-
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PLL Component

• Phase and Frequency Detector (PFD)
• Charge Pump(CP) and Loop Filter
• Self_Biasing Generator and VCO
• Divided_By_20 Circuit
• VCO Output Buffer

Design of Phase and Frequency Detector(PFD)
8
PFD schematic in the PLL
input signal clock
up
input signal dclock
dn
9
PFD simulation results_1
Case_1 input signal clock period is 5ns
and pulse period 2.5ns input
signal dclock period is 4.6ns and pulse
period 2.3ns
dn
up
input signal dclock
input signal clock
10
PFD simulation results_2
Case_2 input signal clock period is 5ns
and pulse period 2.5ns input signal dclock
period is 5.4ns and pulse period 2.7ns
dn
up
input signal dclock
input signal clock
11
PFD simulation results_3

• Case_3
• input signal clock period is 5ns and pulse
  period 2.5ns
• input signal dclock period is 5ns and pulse
  period 2.5ns

dn
up
input signal dclock
input signal clock
12
Layout of PFD
13
Post Layout Simulation when working at 200MHz
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Post Layout Simulation when working at 500MHz
15
Post Layout Simulation when working at 1GHz
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Design of Charge Pump
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Charge Pump (CP)_Current Steering CP with Buffer
When up1, VCP_OUT higher
VCP From Self_Biasing Circuit
2_Stages_OP AMP
VCN From Self_Biasing Circuit
When dn1, VCP_OUT lower
Inverter
18
2_Stages OP_AMP in CP
OUTPUT
INPUT-
INPUT
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Simulation Results of 2 Stages OP_AMP
AC gain
3_dB BW
Phase_Margin(PM)

• AC gain 37dB 3-dB BW 10MHz PM 60 degree

20
The Simulation Setup of Charge Pump and Loop
Filter
Loop Filter
The symbol of charge_pump
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The Simulation Results_1 of The Charge Pump

• Case_1 When up is high and down is zero

The Output Voltage goes higher and higher
up
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The Simulation Results_2 of The Charge Pump

• Case_2 When up is low and dn is high

dn
The Output Voltage goes lower and lower
23
The Simulation Results_3 of The Charge Pump

• Case_3 When PLL is in lock state

up
dn
The output voltage oscilation
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Design of VCO and Self Biasing Circuit
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VCO and Self_Biasing Generator Circuit Design

• Self_Biasing Technique Advantage

• Remove the process technology and environmental
  variability that plagues the PLL design.
• Minimized the supply and substrate noise induced
  jitter.
• The ideal of self_biasing is that it allows
  circuits to choose the operation biasing voltage
  in which they function very well.

26
VCO and Self_Biasing Generator Circuit Schematic
VCP generated for the VCO
VCO output
Vcontr
VCN generated for the VCO
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Each Delay Cell in the 4_Stages Differential VCO

Symmetrical load
VCO
VCP
VCN
VCO-
There exist four identical delay cells in the
4_stages differential VCO
28
The Setup of the Simulation of VCO and
Self_Biasing Circuit
VCO Output
Vcontr From CP
VCO
Star_up circuit
Self_Biasing Generator Circuit
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VCO simulation results_1

• We choose three different cases.one for the
  typical value and two for extreme control
  voltages.

• Case_1 when Vcontrl1.3V .

Centre frequency3.10072GHz

• Transient simulation result
  PSS simulation result

30
VCO simulation results_2

• Case_2 when Vcontrl1.5V .

Centre frequency2.41459GHz

• Transient simulation result
  PSS simulation result

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VCO simulation results_3

• Case_3 when Vcontrl1.0V .

Centre frequency3.97926GHz

• Transient simulation result
  PSS simulation result

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Start Up Circuit in The VCO
Inverter
Vinit
VCN
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Simulation result of Start Up Circuit
VTH0.345443V

• When in the Initial state, the VCN is in the low
  state, i.e0 state and the output is in the high
  state, i.e., nearly VDD and it turns on the
  transistor. When the VCO and self biasing circuit
  works very well and the VCN is in the high state,
  i.e., minimum at least above 0.6V and the output
  of the Startup circuit is in the low state, i.e.,
  the output is nearly close to the gnd. So it will
  automatically stop when VCO works.

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Differential VCO Update

• After post_simulation, The VCO center frequency
  reduced to the 1.8GHz.
• So we re_design the VCO which can work at higher
  frequency,such as 5GHz.

35
The Setup of the Simulation of VCO at 5GHz

• The schematic of VCO and self_biasing circuit

36
The delay cell in the VCO at 5GHz
Delay cell in the VCO
4_stages differential VCO
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Simulation results of VCO at different control
voltage_case 1
Fcenter5.73GHz
When Vcontrl1.4V, The VCO output waveform and
center frequency
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Simulation results of VCO at different control
voltage_case 2
Fcenter5.50GHz
When Vcontrl1.5, The VCO output waveform and
center frequency
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Simulation results of VCO at different control
voltage_case 3
Fcenter4.49GHz
When Vcontrl1.7, The VCO output waveform and
center frequency
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Layout of VCO Delay Cell
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Post Layout Simulation of VCO
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Design of Divided_By_20 Circuit
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Block Diagram of Divided_By_20 Circuit
Differential signal
Vco
Differential to Single End Conversion
Divided-By-2
Divided-By-2
vco
Vco-
Single Ended Signal
To the PFD
Divided-By-5
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The setup of simulation of Divided_by_4 Circuit
DFF-1
DFF-2
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Simulation result of divided_by_4 working at 4GHz
Output waveform of divided_by_4 at 4GHz
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Simulation result of divided_by_4 working at 5GHz
Output waveform of divided_by_4 at 5GHz
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Simulation result of divided_by_4 working at 6GHz
Output waveform of divided_by_4 at 6GHz
48
Layout of Divided_By_4
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Post Layout Simulation(2.7GHz)
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The Differential to Single Ended Signal
Conversion Circuit
Single Output
Input
Input-
NMOS Diff. AMP
PMOS Diff. AMP
INVERTER
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The Simulation Result of Differential into Single
Ended Conversion Circuit
Output from Inverter
Output from PMOS AMP
Input-
Input
Note The differential input signal works at
2GHz.
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Layout of Differential to Single End
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Schematic of Divided_by_4 for Single End Output
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Layout of Single End Divided_By_4
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Post Layout Simulation Results Working at 2.6GHz
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Schematic of Divided_by_5 for Single End Output
Single end DFF( detail schematic seen next page)
Single end divide_by_5 circuit
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Single DFF in the Divider_by_5
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Setup of Divider_by_5 for simulation
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Simulation of the divider_by_5
Output signal
Input signal
When the input signal frequency is500MHz, and
output frequency is 100MHz
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Summary
Output Buffer
For Testing
input signal data 156MHz
up
PFD
Charge_ Pump loop filter
VCO Biasing
Vcontr
dn
input signal dclock
VCO output3.12GHz
VCO
Divided_by_20
VCO-
Work done 1)PFD 2)Charge Pump 3)
Biasing circuit and VCO
4) Divided_By_20 Circuit 5)VCO output buffer

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4.75 GHz CPPLL schematic
Phase and Frequency Detactor
Charge Pump
Self_Biasing VCO
Buffer
Divider_by_20
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Simulation result of divide_by_5
Buffer output
Vco output
Vcontrl
Locking point
down
up
dclock
Data period time
data
The Vcontrl voltage value and locking time when
locking
63
Zoom in the locking range in the simulation result
Buffer output
Vco output
Vcontrl is constant when locking
Vcontrl
down
Up and down ripple is small when locking
up
Rising edge is aligned when locking
dclock
data
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Zoom in the locking frequency in the simulation
result
Output frequency of VCO is 20X as much as input
data frequency
VCO OUTPUT
Vcontrl
Down in the output of PFD
down
UP in the output of PFD
up
Feedback dclock frequency
dclock
Input data frequency
data
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Verification of the PLL working at 4.75GHz
Input voltage1.3723V
Output frequency4.75GHz
Output frequency237.5MHz
66
The simulation result of VCO,BUFFR and
Divider_by_20
The output frequency238MHz,or the period
time4.2ns
Output of divider_by-20
Buffer output
Vco output
So the CPPLL WORKS VERY WELL!
67
Future work

• Optimization system to increase the maximum
  locking frequency.
• Using ADS/MATLAB to determine the phase noise,
  setting time, stability, locking behavior.
• Optimization block and increase these block
  working frequency.
• Using the full differential structure to increase
  the immunity of anti_noise.
• Using the dual loop to increase the locking rate.
• Layout the whole PLL and optimize the whole
  circuit using parasitic simulation.