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Carbon nanotube field effect transistors CNTFETs have displayed exceptional electrical properties su

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Title: Carbon nanotube field effect transistors CNTFETs have displayed exceptional electrical properties su


1
Local-Gated Single-Walled Carbon Nanotube Field
Effect Transistors Assembled by AC
Dielectrophoresis Paul Stokes and Saiful I.
Khondaker Nanoscience Technology Center and
Department of Physics, University of Central
Florida, Florida 32826, USA
RESULTS
INTRODUCTION MOTIVATION
  • Carbon nanotube field effect transistors
    (CNT-FETs) have displayed exceptional electrical
    properties superior to the traditional MOSFET.
  • Most of these fabrication methods for CNT
    electronic devices are based on either random
    positioning or directed assembly by high
    temperature growth on patterned substrate, which
    are not compatible with conventional CMOS
    technologies.
  • Most of these devices are controlled by only a
    global back gate. They do not offer high
    throughput or individual control of each CNT-FET
    necessary for parallel fabrication.
  • For large-scale fabrication of CNT-FET devices
    three conditions need to be satisfied (i)
    separation of semiconducting and metallic carbon
    nanotubes must be realized, (ii) nanotubes need
    to be assembled at selected positions of the
    circuit with high yield, and (iii) each nanotube
    must be addressed individually with a local gate.
  • We present a simple and scalable technique for
    the fabrication of CMOS compatible and local
    gated CNT-FETs from solution. The approach is
    based on directed assembly of individual SWNT via
    AC Dielectrophoresis.

1. Electronic Transport Characteristics of DEP
Assembled Device
4. Comparison to Other DEP and CVD Assembled
CNT-FETs
(a)
(b)
50 Semiconducting
50 Metallic
(a)
(b)
Catalytic Island
b)
5. Electric Field Simulation
Figure 3 Drain current (IDS) - back gate voltage
(VBG) characteristics of representative DEP
assembled metallic (a) and semiconducting (b)
devices (VDS 0.3 V).
(a)
(b)
Figure 1 (a) Random placement of CNT by drop
casting from solution. (b) Patterned growth from
CVD. Requires temperatures of 900 C.
Al2O3
SiO2
2. Electrical Breakdown of Metallic SWNT
METHODS
Au
Au
(b)
(a)
After Electrical Breakdown
Device Fabrication and Dielectrophoretic Assembly
  • Devices were fabricated on heavily doped silicon
    (Si) substrates capped with a thermally grown 250
    nm thick SiO2 layer.
  • Contact pads and electron beam markers were
    fabricated with optical lithography using double
    layer resists, metallization of Cr (5 nm) and Au
    (50 nm) and finally standard lift-off.
  • Source and drain electrode patterns were defined
    with EBL 5 nm Cr and 20 nm thick Au were
    thermally deposited followed by lift-off.
  • 100 nm wide Al gate patterns are defined by EBL
    with 20-25 nm thickness.
  • The sample is treated in oxygen plasma to create
    a thin aluminum oxide dielectric layer.
  • DEP assembly
  • HiPco grown SWNTs (Carbon Nanotechnologies Inc.)
    was ultrasonically dispersed in 5 ml of
    1,2-dichloroethane for approximately 30 minutes.
  • A small drop (8ul) was cast onto a chip with 12
    pairs of source-drain electrodes, each containing
    a 100 nm wide Al gate. An AC voltage of
    approximately 8 VP-P at 1 MHz is applied for 1-2
    seconds.

Figure 6 (a) Electric field simulation between a
1 um gap. Shows that the gradient of electric
field is strongest near the tips of the
electrodes. (b) Plot of the Clausius Mosetti
factor (KF) for SWNTs in dichloroethane. The
force is positive for both semiconducting and
metallic SWNTs up to 5 GHz.
Figure 4 (a) Transformation of a nanotube bundle
into a semiconducting device by selective
breakdown by sequential ramps of VDS (labeled 1
and 2) with back gate set to 10 V. INSET
Resultant current - back gate characteristic
after breakdown (VDS 0.3 V).
CONCLUSION
3. Local Gate Characteristics
(a)
  • We have fabricated CNT-FETs with local Al bottom
    gates through DEP.
  • Our method offers a convenient way to assemble
    local-gated CNT-FET devices from solution without
    the need of high temperature growth, making it
    compatible with present microfabrication
    technology.
  • Our local-gated devices show superior
    characteristics such as small values of threshold
    swing and low threshold voltage compared to other
    DEP assembled back gated CNT-FETs.
  • Local gating offers fast switching behavior due
    to the channel controlled mechanism owed to the
    thin local Al gate.
  • Directed assembly of local gated CNT-FETs at
    selected position of the circuit via DEP may pave
    the way for large scale fabrication of CMOS
    compatible nanoelectronic devices.

(b)
Au
Au
Au
Au
(b)
(a)
SiO2
SiO2
Back Gate
Si
Si back gate
1MHz, 8Vp-p
Al/Al2O3 local gate
(c)
(d)
Local Gate
REFERENCES
HiPCO SWNTs
  • Tans et al., Nature, 393, 49 (1998).
  • Kasper Grove-Rasmussen, University of Copenhage,
    Denmark, PhD thesis (2006).
  • Dong et al, J. Phys. Chem. B 109 13148 (2005).
  • Lin et al, IEEE Elec. Dev. Lett. 26 823 (2005).
  • Javey et al, Nature Mater. 1 241 (2002).
  • P. Stokes and S. I. Khondaker, Nanotechnology 19
    175202 (2008).

Figure 5 (a) IDS versus VLG and VBG for
comparison form the same device after DEP
assembly. Local gate shows far better gate
coupling. INSET Expanded plot of IDS vs. VLG
showing low threshold voltage and subthreshold
swing. The gate leakage current is lt 1 pA. (fast
switching is possibly due to channel controlled
operation). b) Output characteristics, for
different gate voltages up to the saturation
regime.
Figure 2 Fabrication of local gated CNT-FET
device. (a) Source (S) - drain (D) electrodes of
1 µm separation are patterned. (b) Local Al/Al203
gate electrodes are patterned using EBL. (c) DEP
assembly of CNT from solution. (d) AFM image of a
device showing nanotubes are assembled at the
tips.
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