Beyond the Red Brick Wall: Physical Design Challenges at 50nm and Below

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Beyond the Red Brick Wall Physical Design
Challenges at 50nm and Below

• Andrew B. Kahng
• UC San Diego, Depts. of CSE and ECE
• abk_at_ucsd.edu
• http//vlsicad.ucsd.edu (http//vlsicad.cs.ucla
  .edu )

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What is NOT a Physical Design Challenge?

• Problems that are beyond PD scope / control
• Finding high-k dielectric materials
• Creativity (e.g., AMS/RF circuit innovations)
• We are in the automation (not the creativity)
  business
• Problems whose instance sizes and solution times
  scale with power of available computing platforms
• Most analyses (static timing, SI, dynamic
  simulation, )
• Assumption methodology will be applied
  (filtering, incr / ECO, hierarchy,
  divide/conquer, abstracts, guardbanding, )
• In future, commodity syntheses
• Scalable Engines (free) Commodities
• (multilevel paradigm) Place, Perf Opt, Logic
  Synth, Route,

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Primary Driver at 50nm System Cost

• NRE Cost for Design
• TAT driver for Methodology
• http//www.eda.org/edps
• Cost of Design Technology not so
  well-understood
• Application-Specific CAD (e.g., high-volume
  custom vs. SOC)
• Design Technology Productivity Roadmaps,
  Reuse, Metrics
• IEEE Design and Test Special Issue, Nov-Dec 2001
  ITRS-2001 effort
• NRE Cost for Manufacturing
• Manufacturing Cost
• Design for Cost-of-Manufacturing
• Variability and Die-Package-Board interactions

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Complementary Driver at 50nm System Value

• Quality of Design Value of Design
• Speed, Reliability, Parametric Yield,
• Key Issue 1 Power
• Speed-power fundamental tradeoff
• Static power dissipation, power distribution,
• How to avoid battery weight, use of advanced
  forced-air and chilling,
• Key Issue 2 Synchronization and Global
  Signaling
• Fundamental clocking limits, latency-insensitive
  design methodology,
• Issues that are NOT driving PD
• Litany UDSM TSIIRGBLEMSHHEEMISEU

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1. TAT Closing the Synthesis-Analysis Loop

• How we handle this loop the heart of
  methodology
• E.g., Correct by Construction (assume/enforce,
  predict/enforce, )
• E.g., Construct by Correction (tool, data
  model, DB for tight S/A loop)
• Syntheses must have true estimation capabilities
• Syntheses must be driven by most-appropriate
  abstractions or approximations of Analyses
• How much is left on the table depends on two
  things
• How well do we make methodology choices? (Space
  / shield / rpt / size ? Optimization / layout /
  synthesis loop structure?)
• How well do we identify objectives for engines in
  PD? (e.g., FP, GPlace)
• Greatest leverage Chip planning (block
  shaping/placement, interconnect planning)
• Very important to work on right problems with
  right goals
• Cf. ISPD-2000 talk on floorplanning

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2. Cost Closing the Design-Manufacturing Loop

• Silicon mindset
• ECAD / Mask / Mfg merged infrastructures
• Variability improved taxonomy and criteria

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What does EDA know about process today?
ECAD
Design
Device models Design rules

• Process
• Develop.
• Lithography
• Device

GDSII
Clean Abstraction As Little as Possible
Next to Nothing
TCAD
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What Must EDA Know Tomorrow?
Useful Abstraction As Much as Possible
ECAD
Process Requirements
Design
Device models Design rules
GDSII, tolerances,...

• Process
• Develop.
• Lithography
• Device

Mask
tolerances...
Devl. Fab
Production Fab
TCAD
Semi suppliers
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PSM in 180nm Library Cell
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Field-Dependent Aberration

• Field-dependent aberrations cause placement
  errors and distortions

R. Pack, Cadence
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Example Challenges

• Function-aware OPC/PSM/Fill insertion
  (corrections)
• Layout corrections are for predictable circuit
  performance, function
• Tools should understand functional intent, make
  only the corrections that win , reduce
  performance variation
• Applies to mask inspection also
• Cost-aware corrections
• Dont make corrections that cant be manufactured
  or verified
• Understand costs of each correction (data volume,
  yield costs, verification costs, etc.)
• Solutions to (difficult) flow issues
• how to avoid making same correction 3x (lib,
  router, PV tool)

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Some Variability Analysis Needs

• Taxonomy
• Static t_ox, V_t, L_eff,
• Dynamic V_dd, rho,
• Instance interconnection topology and embedded
  length distribution,
• Correctable vs. uncorrectable
• Distinguish primary vs. derived variabilities,
  e.g., dopant / Idsat
• Model back to root causes, e.g., registration
  error, microloading
• Model the context, e.g., vias, dielectrics,
  critical paths
• Model correlations and anti-correlations (e.g.,
  dimensions of line vs. space, line vs. ILD)

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3. Closing the Design Technology Productivity
Gap

• Design Productivity Gap
• huge cost to semiconductor industry
• Traditional perspective change the Design
  Problem, invent new algorithms, ...
• New perspective Design Productivity Gap
  Design Technology Productivity Gap
• Problem Improve Time-To-Market and
  Quality-of-Result for Design Technology
• New goal Improve how we specify, develop, and
  measure and improve Design Technology (PD is a
  good place to start)

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Aspects of the Design Technology Gap

• No Roadmap
• Time-to-Market 5-7 yr to get new algorithm
  into production Time-to-Market No reuse in
  design technology
• Lack of Foundation CAD-IP
• Over-resourcing of non-strategic technology
• QOR difficult to evaluate impact of new tools,
  new research on overall design process
• Lack of standard metrics (especially cost
  metrics) for design technology, design process
• If you cant measure it, you cant improve it !!!

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New Infrastructure is Needed to Answer

• Improved vision and design technology planning
  (specify)
• What will the design problem look like?
• Accurate roadmapping for Design Technology
• Application-Specific Design Technology
  (cost-driven)
• Improved execution (develop)
• How can we quickly develop the right technology
  (TTM)?
• Reusable, commodity, Foundation CAD-IP
• Improved measurement (measure and improve)
• Did we solve the problem (QOR)? Did the design
  process improve?
• Design tool/process metrics, design process
  instrumentation
• Design Technology Productivity will improve
  Design Productivity

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Optical Proximity Correction (OPC)

• Corrective modifications to improve process
  control
• improve yield (process latitude)
• improve device performance

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Macroscopic Process Effects
Dummy Fill controls several types of process
distortions
CMP, SOG
RIE
CVD
R. Pack, Cadence
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Direction for Development - PSM

• New logic (mapping) and performance optimization
  formulations
• with phase shifting, gate lengths and wire widths
  continuously variable between b and B
• without phase shifting, gate lengths and wire
  widths must be at least B
• not all features can be phase-shifted
  function-driven
• What is optimal choice of phase-shifted
  features, and their sizes?

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Direction for Development - PSM

• Understand PSM implications for custom layout
• define a taxonomy of phase conflict
• no set of traditional design rules can handle all
  phase conflicts what are good layout
  practices?
• no Ts on poly
• fingered transistors should have even-length
  fingers
• etc.
• Address PSM as a multi-layer problem
• e.g., conflict can be solved by re-routing a
  connection to another layer

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Directions for Development Pattern Fill

• Practical criteria
• No cleavage lines Probeability Multiple
  length scales Simultaneous control of fill
  area/perimeter etc.
• Hierarchical filling
• Grounded fill generation
• Multi-layer density control
• RCX/TA flows (with PR)