Muon Track-Finder Trigger

1
Muon Track-Finder Trigger

• Darin Acosta
• University of Florida
• May, 2003

2
CSC Muon Trigger Scheme
EMU
Trigger
On-Chamber Trigger Primitives
Muon Port Card(Rice)
3-D Track-Finding and Measurement
Trigger Motherboard(UCLA)
Strip FE cards
Sector Receiver/ Processor(U. Florida)
LCT
OPTICAL
FE
SP
SR/SP
MPC
LCT
3? / port card
TMB
FE
2? / chamber
3? / sector
Wire LCT card
Wire FE cards
In counting house
RIM
CSC Muon Sorter(Rice)
RPC Interface Module
DT
RPC
4?
4?
4?
Combination of all 3 Muon Systems
Global L1
Global ? Trigger
4?
3
Muon Track-Finding

• Link trigger primitives into 3D tracks
• Measure pT, ?, and ? in non-uniform fringe field
• Send highest quality candidates to Global Trigger

• Partitioned into 60 sectors that align with
  DT chambers

?
?
4
Basis of Track-Finding Logic

• h Road Finder
• Check if track segment is in allowed trigger
  region in h.
• Check if Dh and h bend angle are consistent with
  a track originating at the collision vertex.

1
2
2

• f Road Finder
• Check if Df is consistent with f bend angle fB
  measured at each station.
• Check if Df in allowed range for each h window.

1

• Quality Assignment Unit
• Assigns final quality of extrapolation by looking
  at output from h and f road finders and the track
  segment quality.

Extrapolation Units utilize 3-D information for
track-finding.
5
PT Measurement
Df
Pt LUT 4 MB
Can use information from up to 3 chambers
2
PT
1
Pt f(Df12, Df23 , h )
IP
Residual Plot
Constant Pt Contours for 3, 5 ,and 10 GeV ms.
Res22
6
L1 Trigger Table (L21033)
Only (endcap) muon triggers have low enough
thresholds to allowa B-physics program at CMS in
addition to the high PT physics
7
Trigger is Extensible
ME1 ME2 ME3 ME4
X
X
X
Single TeV m Events with neutron background
Without ME4/1 e 72 With AU
Corrections e 86.3 De/e 20
X

• With re-scope of ME4/1, trigger logic can be
  modified to take advantage of redundancy and
  remove bad hits (hardware I/O can always accept
  ME4)
• Improvement in acceptance and PT assignment
  yields 20 increase in efficiency in forward
  region

?
8
1st Prototype Track-Finder Tests
Clock Control Board (Rice)
Sector Receiver (UCLA)
Muon Port Card (Rice)
Sector Processor (Florida)
SBS VME Interface
Very successful, but overall CSC latency was too
high New 2002 design improves latency
Custom ChannelLink Backplane (Florida)
Results included in Trigger TDR (2000)
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CSC Track-Finder Crate
Second generation prototypes



Clock and Control Board

Sector Processor


SR

SR

SR

SR

SR

SR

SR

SR

SR

SR

SR

SR


CCB
/
MS
/

/

/

/

/


/

/

/

/

/

/



SP
SP

SP

SP

SP

SP


SP

SP

SP

SP

SP

SP

From MPC

SBS 620 Controller
(chamber 4)

Muon Sorter
From MPC

(chamber 3)


From MPC


(chamber 2)

From MPC

(chamber 1B)


From MPC


(chamber 1A)


To DAQ

Single Track-Finder Crate Design with 1.6 Gbit/s
optical links Custom 6U GTLP backplane for
interconnections
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Combined SR/SP 2002

• Delays with complex layout using in-house tools
• Sent to industry for completion of layout using
  Cadence Allegro
• Final board takes 16 layers
• 3 boards manufactured and stuffed

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SP2002 Main Board (SR Logic)
DC-DC Converter
EEPROM
Phi Global LUT
VME/CCB FPGA
Eta Global LUT
Phi Local LUT
TLK2501 Transceiver
To/from custom GTLP back-plane
Front FPGA

• Optical Transceivers
• 15 x 1.6 Gbit/s Links

3 SRs
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SP Trigger Logic
From SP2000 to
SP2002 mezzanine card
(5
manufactured)
Xilinx Virtex-2 XC2V4000800 user I/O
(Mezzanine card is also used for CSC sorter)
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Tests underway
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Optical Link Tests

• Currently we are testing 3 optical links in a MPC
  to SP chain test
• One test uses the pseudo-random number test built
  into the TLK2501 chipset
• Another uses software that downloads data into
  the MPC buffers and explicitly reads out and
  compares the data received by the SP
• The CCB is used for control and clock signals
• Software, firmware, and tests are still ongoing

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Remaining Crate Tests Foreseen

• SP ? SP optical link (all 15) tests
• SR LUT memory tests
• SP track-finding logic tests (mezzanine card)
• Multi-MPC to SP crate tests
• SP ? Muon Sorter crate tests
• SP ? EMU DAQ board (DDU) tests
• SP ? DT Track-Finder interface tests
• These tests are expected to take place during
  this summer and Fall

16
Beam Test Plans

• Plan to test CSC Trigger all the way to the
  Track-Finder in beam tests at CERN during
  May/June
• Complete chain test from 2 detectors to
  peripheral crate electronics to Track-Finder
  crate electronics!
• Our goal is to validate that trigger primitives
  are found efficiently on correct BX and
  successfully received over optical links
• Record as much data as possible under various
  detector configurations for future track
  identification studies

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Personnel

• Professors
• Darin Acosta (Florida), Robert Cousins (UCLA),
  Jay Hauser (UCLA), Paul Padley (Rice)
• Postdocs
• Sang-Joon Lee (Rice), Holger Stoeck (Florida),
  Slava Valouev (UCLA), Martin Von der Mey (UCLA),
  Song Ming Wang (Florida)
• Students
• Brian Mohr (UCLA), Jason Mumford (UCLA), Greg
  Pawloski (Rice), Bobby Scurlock (Florida),
• Engineers
• Alex Madorsky (Florida), Mike Matveev (Rice),
  Ted Nussbaum (Rice), Alex Tumanov (Rice -
  Software)
• Collaborating engineers (PNPI)
• Victor Golovtsov, Lev Uvarov