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332:578 Deep Submicron VLSI Design Lecture 23 Latchup and Reliability


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Title: 332:578 Deep Submicron VLSI Design Lecture 23 Latchup and Reliability

332578 Deep Submicron VLSI Design Lecture 23
Latchup and Reliability
  • David Harris and Mike Bushnell
  • Harvey Mudd College and Rutgers University
  • Spring 2005

Material from CMOS VLSI Design By Neil E. Weste
and Harris
  • Reliability CMOS reliability failures due to
  • Electromigration
  • Self-heating
  • Hot Carriers
  • Latchup
  • Latchup Prevention
  • Overvoltage
  • Time-Dependent Dialectric Breakdown (TDDB)
  • DRAM Soft Errors
  • Summary

  • MTBF Mean Time Between Failures
  • MTTF Mean Time to Failure
  • FIT Failures in Time 109 X (failure
  • Good value is 1000 FIT or 1 failure in 114 years
    for 1 chip
  • Example
  • System has 10-0 chips rated at 1000 FIT
  • Customer purchases 10 systems
  • Failure rate 100 X 1000 X 10 106 FIT
  • One failure every 1000 hours (42 days)
  • Must keep FIT less than 100 FIT

  • Due to electron wind in wires
  • Big problem in Al wires less troublesome in Cu,
    Al-Cu, or Al-Si wires
  • Due to different grain transport properties
  • Depends on current density J I / wt
  • More likely in DC wires than in AC wires
  • Jdc is electromigration limit should be lt 1 to
    2 mA/mm2 at T 110 C
  • Ea is defect activation energy

  • High currents dissipate power in wire, raise its
  • Hot wires have greater R and delay
  • Self-heating also speeds up electromigration
  • High but brief peak currents can even melt wires
  • Self-heating depends on RMS current density
  • Keep Jrms lt 15 mA/mm2 for Al
  • Particularly bad for SOI -- poor thermal
    conductivity of SiO2

  • Mainly a problem in power and ground
  • Causes problems in gates, too
  • Fix by widening lines or reducing transistor sizes

Hot Carriers
  • During switching, e-- injected into gate oxide
    and get trapped
  • Changes I-V device characeristics
  • Reduces I in nFETs, increases I in pFETs
  • Maximum damage when Isub is large, nMOSFETS are
    in saturation, and input rises
  • Worst for inverters and NOR gates for high
    supply voltages

Wearout from Hot Carriers
  • Makes nFETs too slow
  • Causes sense amps. and matched circuits to fail
  • Matched components degrade differently
  • Limit wear by limiting max. input rise time and
    stage electrical effort
  • Negative Bias Temperature Instability (NBTI)
  • Decreases pFET current as pFETs wear
  • Due to trapped holes in oxide coupled with
    interface state creation
  • Causes circuit failure due to delay and mismatch
  • NBTI depends on device electric field

  • Causes shorting of VDD VSS lines
  • Result
  • Destroys chip or
  • Causes system failure must power down to fix
  • Control with process innovations circuit design
  • Thyristor circuit embedded in every CMOS logic

Parasitic Transistor Location
Equivalent Analog Circuit
Latchup Failure Mechanism
  • Draw current through substrate Vsub rises
  • Emitter-Base voltage drop becomes 0.7 V.
  • npn transistor turns on current flows in well
  • Base-Emitter voltage of pnp transistor rises
  • pnp transistor turns on when Vbe -0.7 V
  • npn Base voltage raises due to positive feedback
  • At npn base-emitter voltage trigger point
    emitter voltage snaps back and thyristor turns on
  • Stays on as long as V across 2 transistors gt
    holding voltage
  • Terminals go to 4 V. and metal lines supplying
    latched-up circuit burn out

Latchup Triggering
  • Must trigger parasitic npn pnp circuit
  • Must maintain holding state
  • Trigger with transient currents or voltages
  • During power-up
  • External signals beyond operating ranges
  • Trigger with radiation pulses

Lateral Triggering
  • Current flows in emitter of lateral npn bipolar
  • Intrigger Vpnp-on
  • anpn Rwell
  • Vpnp-on 0.7 V
  • anpn common base gain of lateral npn
  • Rwell well resistance

Vertical Triggering
  • When enough current is injected into emitter of
    vertical pnp
  • Like lateral case
  • Current gets multiplied by common base gain
  • Causes voltage drop across emitter-base junction
    due to Rsubstrate
  • Holding (or sustaining) point
  • Stable operating point if current can be
  • Needed current injection unlikely to be caused
    by supply voltage transients, except in CMOS pad

Latchup Scenarios
  • Whether latchup occurs depends on
  • Pulse widths
  • Speed of parasitic transistors

Latchup Scenario 1
Undershoot output dips below VSS by gt 0.7 V
latches up
Latchup Scenario 2
  • pMOS overshoots VDD by gt 0.7 V

Latchup Prevention
  • Latchup happens with
  • bnpn bpnp gt 1 (bnpn 1) (IRsubs IRwell
  • IDD
  • IRsubs Vbe npn
  • Rsubs
  • IRwell Vbe pnp
  • Rwell
  • IDD Supply current (total)

Solutions to Latchup
  • Solutions
  • Reduce R values
  • Reduce bipolar transistor gains
  • Prevention
  • Latchup-resistant CMOS processes
  • Layout techniques

  • Si starting material, thin epitaxial Si on top of
    heavily doped substrate
  • Decreases substrate R
  • Sinks collector I of vertical pnp
  • The thinner the epi the better
  • Retrgrade well structure
  • Well bottom highly doped, top is more lightly
  • Gives good transistors but reduces R deep in the
  • Can increase holding V. above VDD
  • Hard to reduce bs bpnp 10 to 100, bnpn 2 to

Internal Latchup Prevention
  • Use merged substrate/source contacts
  • Reduces Rsubs and Rwell
  • In most processes, latchup cannot happen if you
    use liberal substrate contacts
  • Every well needs a substrate contact
  • Connect each substrate contact through metal
    directly to a supply pad
  • Put substrate contracts as close to source
    transistor connection on the supply rail as
  • Conservative use 1 substrate contact for every
    supply connection

Internal Latchup Prevention (contd.)
  • Put a substrate contact for every 5-10
    transistors or every 25 to 100 mm
  • Pack n devices toward VSS, and p devices toward
  • Avoid checkerboard transistor arrangements

I/O Latchup Prevention
  • Very susceptible to latchup external voltages
    ring below GND or above VDD
  • Use guard rings
  • These spoil the parasitic bipolar devices by
    collecting minority carriers
  • Area penalty high, but must be used in outer
    space electronics to avoid radiation-induced
  • Not so bad if you do this only for I/O drivers

I/O Guard Rings
I/O Guard Rings
Guard Ring Structure
n-Well Process Latchup Prevention
  • Use proven I/O structures
  • Physically separate n p transistors with the
    bonding pad
  • Put n (p) guard rings shorted to VSS (VDD)
    around p (n) transistors
  • Place source diffusion regions along
    equipotential lines for current flowing from VSS
    to p Well
  • Make source fingers perpendicular to current flow
  • Short n transistor source to substrate p
    transistor source to n-well with metal along
    entire length

n-Well Process Latchup Prevention
  • Hard-wire n-well to power (via n) to divert
    injected charge to VDD
  • Keep spacing between n-substrate p transistor
    source contact minimal (collects minority
  • Keep spacing between substrate p and n
    transistor source contact minimal
  • All diffusion areas connected to external world
    must be surrounded by guard rings
  • SOI processes completely avoid latchup no
    parasitic bipolar transistors
  • If VDD lt 0.7 V, parasitic bipolar transistors
    never turn on

Overvoltage Failure
  • Due to
  • Electrostatic discharge (ESD)
  • Oxide breakdown
  • Punchthrough
  • Time-dependent dielectric breakdown of gate oxide
  • Cause
  • Breakdown arcing across thin oxide
  • Exists maximum safe voltage for transistors
  • Often less than I/O standard voltage
  • Requires 2nd transistor type with thicker oxides
    and longer channel to handle higher I/O voltage

Time-Dependent Dielectric Breakdown (TDDB)
  • Gate oxides wear out due to damage from tunneling
  • Exponential dependent on T and tox
  • For 10-year life at T 125 C
  • Field across gate Eox lt 7 MV/cm 0.7 V/nm
  • Greatest problem during voltage overshoots
  • Noisy power supplies
  • Reflections on I/O pads

Soft Errors
  • In 1970s, DRAMs sometimes flipped bits for no
  • Linked to alpha particles and cosmic rays
  • Collisions with particles create substrate e--
    hole pairs
  • Carriers collected on dynamic nodes, disturbing
    the voltage
  • Minimize soft errors by having plenty of charge
    on dynamic nodes
  • Tolerate errors through ECC, redundancy
  • Particularly a problem with flip-chip technology
    due to radioactive decay from lead in solder
  • Use aged lead and highly-purified Al wires

  • Reliability
  • Electromigration
  • Self-heating
  • Hot Carriers
  • Latchup
  • Latchup Prevention
  • Overvoltage
  • Time-Dependent Dialectric Breakdown (TDDB)
  • DRAM Soft Errors
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