Title: Original Co-Design of VASP, a Space Qualified Mixed-Signal ASIC by Space Industry
1Original Co-Design of VASP, a Space Qualified
Mixed-Signal ASICby Space Industry Consumer
IP provider
2AGENDA
- HIVAC project to provide a versatile Video Signal
Processor VASP - Selection of a technology for VASP
- From hardening guidelines
- to design hardening (100 CHIPIDEA , 6 slides
report the hardening handling at design level) - Qualifying and quantifying radiation hardness of
VASP - Analog intellectual property and reusability of
analog circuits in space conditions for success
3HIVAC project
- HIVAC project is an ESA co-funded project
- contract n19872/06/NL/JA
- Phase 1 (Specification - Architecture
Feasibility - Technology selection) - 07/2006 to 07/2007
- Phase 2 (Detailed Design and Tests)
- on-going since 12/2007
- Prototypes planned for beginning of 2009
- Results planned before end of 2009
- This project is based on innovative organization
of partnership between - THALES ALENIA SPACE, as prime contractor, is the
European leader for Satellite Systems and since
1993 the company has been designing and
developing an important series of space used
Mixed-Analog ASICs. THALES ALENIA SPACE is a
major actor in the field of camera detection
electronics for Earth Observation and Scientific
missions. - CHIPIDEA-MIPS Analog Business Group, as design
partner, is a world leading analog/mixed-signal
intellectual property provider. CHIPIDEA does not
have experience in design hardening.
4HIVAC project
- HIVAC project is aiming at the design, the
development and the validation of a high
performances video signal processing ASIC namely
the Video Acquisition Signal Processor (VASP) and
related module (HIVAC) accommodating CCD and CMOS
detectors
5HIVAC project
- VASP design is based on high performances analog
block functions for signal conditioning and
digital block functions for SpaceWire RMAP signal
interfacing
Main VASPs specifications Power
Supply 3.3V CCD and CMOS detector
compatibility Pixel frequency 0.1Mhz to 3Mhz ADC
resolution 16 bits INL lt 1LSB DNL lt
0.5LSB Total noise at unity gain 2 LSB
RMS Programmable gain from 1 to 8 Spacewire
Interface _at_ 100Mbps min Consumption 350mW
typ Latch-up immunity gt 70Mev/mg/cm² LET TID
hardness gt 50Krad(Si) Package is CQFP 164 pins
6HIVAC project
- Technical challenge due to the high level of VASP
required performances high resolution analog
processing high speed digital on the same chip
space hardened - Organization challenges to share the best
know-how from each partner to succeed - video signal processing for space application
- radiation hardening
- high performances analog and mixed design
- THALES ALENIA SPACE tasks
- Requirements for VASP and HIVAC module
- Technology survey. The final selection is made
with agreement of ESA and MIPS / CHIPIDEA - Hardening guidelines and support for
implementation - Support for radiation characterization
- HIVAC module design, manufacturing and validation
- Validation of VASP in the HIVAC module
- MIPS / CHIPIDEA tasks
- VASP ASIC design architectural analysis,
detailed mixed design - Prototypes procurement (MLM foundry foreseen)
- Electrical Tests and characterization
7Selection of a technology for VASP
- No qualified mixed technology is available !
- A pragmatic approach agreed with ESA and CHIPIDEA
to select the technology for VASP - Identify all accessible technologies via
european MPW centers or known partners - Short list of 7 technologies max to avoid a too
wide analysis european source, 3.3V power
supply, digital density, maturity - 6 groups of criterion having there own relative
weight - Analysis and notation of each short listed
technology - Final choice in the 3 technologies having the
higher notation
8Selection of a technology for VASP
- Short listed technologies
- Mainly CMOS 0.35µm 0.35µm are very mature
technologies used for commercial growing markets
such as medical and new generation automotive.
The perenniality is high because 0.35µm appears
to be the CMOS basic standard for High Voltage
compatible technologies (smart power, smart
sensors, etc). Finally, because widely
available, it guarantees a probable good level of
portability of the design.
9Selection of a technology for VASP
- Selection criterion
- Accessibility
- Foundry nationality, Process perenniality, Low
volume production access - Low cost prototyping
- Prototyping foundry type (MPW, MLM), Number of
MPW runs / year, Delay for prototypes delivery,
Prototyping costs (based on a VASP figure) - High-reliability Low volume production and
Qualification - Available back-end resources, Low volume silicon
production and qualification costs (based on a
VASP figure) - Technical Characteristics
- Process characteristics versus radiation (EPI
substrate, retrograde wells, buried layer,
salicidation, substrate isolation option, oxides
thickness), temperature range, simulation models
temperature range, electrical performances of
MOS, RES, CAP, digital integration - Radiation environment
- Existing radiation characterization (TID, SEL and
SEU) - Design Kit and models
- Compatibility with CHIIDEA and THALESs EDA flow
(analog, digital and mixed) - Availability of enough accurate models for MOS
(BSIM3, MM9) for fine analog simulation
10Selection of a technology for VASP
- 3 technologies having the higher notation 1/3
- STM BICMOS6G
- This technology is very mature and perennial
STM doubled the production in 2007. STM provides
prototyping with MLM (no MPW available directly
with STM). - STM BICMOS6G could be the best guarantee for
space environment withstanding and HR back-end.
STM proposes (with charge) a process improvement
that allows to shift TID from 100krad to 300krad
for digital. - STM BICMOS6G cannot be selected as baseline for
VASP regarding MPW run stop on 2008 (through
CMP) and higher costs for low volume production. - Even if it involves higher costs, direct foundry
and back-end via STM allow risk sharing (i.e. in
case of quality problem on wafer or during
back-end).
11Selection of a technology for VASP
- 3 technologies having the higher notation 2/3
- XFAB XH035
- This high voltage technology offers a wide range
of potential application, including a good
compatibility to handle obsolescence of 5V analog
ASIC (i.e. availability of 5V mos, vertical PNP
and vertical isolated NPN). - Direct access to XFAB or via partners offers
suitable flexibility (MPW (4 runs/year, MLM) even
if not accessible via MPW centers. The MLM at
reasonable cost could be very interesting
regarding schedule constraints. - The availability of the design kit in most
popular tools environment (CADENCE, MENTOR,
TANNER, SYNOPSYS models) allows a wide range of
cooperation with university, laboratory, small
company, etc - Low cost MPW access is available with XFAB but
cannot be used several times if no volume is
ordered (min 24 wafers) it is clear that XFAB
do not want to make business with only MPW or
MLM. However, a scheme as 1 or 2 MPW one lot of
24 wafers for FM production could be acceptable
(no commitment for lot foundry is required to
access MPW or MLM run).
12Selection of a technology for VASP
- 3 technologies having the higher notation 3/3
- AMIS I3T80
- The technical choice of AMIS I3T80 by SODERN for
SPADA in a previous project (cf AMICSA 2006)
confirms that 0.35µm CMOS is a good technological
target. The DK developed for TANNER by SODERN is
not yet available (distribution via EUROPRACTICE
under analysis) and it does not cover the digital
cells. - Furthermore, for a complex mixed design as VASP,
TANNER cannot be considered as a suitable
verification and extraction tool regarding the
other widely used tools (CALIBRE, ASSURA) - I3T80 does not provide HSPICE analog models.
- Due to its incompatibility with CHIPIDEAs tools
(cf HSPICE), AMIS I3T80 is not proposed as a
backup technology.
13Selection of a technology for VASP
- STM BICMOS6G
- From a technical point of view, taking into
account all available information, BiCMOS6G is
the only one technology fulfilling all space
application need (environment withstanding and HR
backend). However, BiCMOS6G cannot be selected as
baseline technology in the frame of VASP/HIVAC
contract because of costs and perenniality of MPW
access through CMP. - XFAB XH035
- By making the best trade-off between cost,
technical characteristics, technology and access
perenniality, risk regarding space environment
withstanding, XFAB XH035 is selected to be the
baseline for VASP design.
14From hardening guidelines
- Hardening approach
- The technology for VASP design (XFAB XH035) has
not been fully qualified for space environment
(only total dose tested up to 107krad on an
analog design). So the effective withstanding of
a complex mixed design can not be guaranteed. - So, à priori hardening by design techniques
shall be used to minimize as much as possible the
risk on space environment withstanding. - THALES ALENIA SPACE provided to CHIPIDEA
hardening guidelines covering the following
aspects, at several levels design kit
configuration/adaptation, architecture, cells
design, layout, elementary cells - Description of Radiation Effects charge
accumulation in oxide, single events - Hardening at digital design level
- Hardening at analog design level
- Hardening example (a band-gap and its AOP)
- Radiation testing TID, SE following ESCC 9000
standard - THALES ALENIA SPACE provided to CHIPIDEA Design
Kit adaptation (and its related user manual) to
handle ELT MOS layout example (ELT MOS,
inter-digitized differential pair and mirror),
EXTRACTION and LVS rules, representative
simulation models. - THALES ALENIA SPACE provides support to CHIPIDEA
during the overall project at architecture,
design, simulation and layout levels, electrical
test, TID test, SE test.
15From hardening guidelines
- Hardening at digital design level
- TID use of the standard cells, excluding all
gates having more than 3 serial MOS - SEL the junction isolated standard cells
library (low noise) is selected because providing
a possible intrinsic SEL immunity. IOs layout
will be improved. - SEU FSM implementation, TMR, EADC for RAM
- SET 0.35µm technology is considered SET
insensitive - A set of standard cells are forbidden internal
tri-state, flip-flop without reset, etc - Floor plan insert guard rings with highest
contact density - Hardening at analog design level
- hardening from architectures trade-off to layout
- TID and ELDRS in bipolar
- SET limited bandwidth, switched capacitor
design, saturation recovery - TID in MOS design margins to reduce VT drift
impact, ELT MOS to suppress bird-beak effect - Forbidden analog cells lateral bipolar
transistors, P diffusion resistors - Layout systematic use of ELT MOS, systematic
guard ring strategy
16From hardening guidelines
- Hardening example a band-gap designed by
CHIPIDEA has been hardened by THALES ALENIA SPACE
at beginning of design phase to be used as good
practice design example - hardening by design does not disturb performances
Hardened Band-Gap
Hardened Band-Gap
Original Band-Gap
Original Band-Gap
Band-gap voltage f(power-supply (3.3V 5))
Band-gap voltage f(temperature)
17 to design hardening
- Design Kit adaptation to handle ELT MOS
- Layout development of a parameterized PCELL
following THALES example - Layout example for inter-digitized differential
pair and mirror, - EXTRACTION and LVS rules,
- Representative simulation models,
- User manual
- Encountered difficulties with design-kit
- Some pcell bugs in the design-kit DMIM
capacitor, Hrpoly resistor - Design kit frequently updated (3 times / year)
- Requires analysis to decide to follow or not is
the used subset of cells impacted ? - Requires update of rules files (integration of
ELT MOS) difficult process to get the source
files from XFAB (only compiled rules delivered in
design-kit) - We decided to stick during the whole project to
the version 3.0.5, issued in November 2007
18 to design hardening
- Analog Design Hardening Constrains
- ELT MOS
- Limits minimum W/L of transistors
- Increases charge injection due to non-minimum
devices - To limit charge injection non-minimum capacitors
had to be used in switched capacitor circuits - Non symmetrical device requires careful circuit
orientation, and provides one low parasitic
capacitance node (the internal one) that can ease
design performances - Increases area
- Increases consumption
- Minimum branch current in a device
- Increase power due to higher parasitic
capacitance - Increases area to keep ELT MOS with minimum
overdrive voltage - Vt voltage drifts
- Biasing, gain, GBW margins
- Drive Comparators architecture choice and
operating
19- Analog Design Hardening Constrains
- Layout
- Increases area guard rings, minimum number of
contacts (reliability) - Design kit adaptation for hardening only
available with Diva rules - DRC and LVS of top layout done with macro blocks
- No extraction rules for RCX, only parasitic
capacitance
20- Digital Design Hardening Constrains
- TMR insertion in registers, EDAC on RAM blocks
- FSM encoding, avoid blocking states
- Automated process to ensure a reproductible
process for synthesis, TMR insertion, timings
extraction and placeroute - TMR increases area and power
- Increases delay in data signals, more load on
clock tree - Low noise Standard cell choice limits maximum
clock frequency in Space Wire (100Mbps) - As a consequence at VASP chip level
- Estimated device area is high 85 mm2
- Power consumption target can not be reached.
- Space Wire data rate is limited at 100Mbps
21Qualifying VASP
- Qualification according to ESCC Generic
Specification No. 9000 (1/6) - Chart F 1 - General Flow chart for VASP ASIC
procurement
VASP could be delivered as qualified packaged
component or naked dice
22Qualifying VASP
- Qualification according to ESCC Generic
Specification No. 9000 (2/6) - Chart F 2 - Production Control
23Qualifying VASP
- Qualification according to ESCC Generic
Specification No. 9000 (3/6) - Chart F 3 - Screening Tests
24Qualifying VASP
- Qualification according to ESCC Generic
Specification No. 9000 (4/6) - Chart F 4 - Qualification and Periodic Tests
25Qualifying VASP
- Qualification according to ESCC Generic
Specification No. 9000 (5/6) - Chart 5 - Flow Chart for Radiation (TID)
Qualification and Lot Acceptance Testing
- At low dose rate
- 36 rad(Si)/h lt dose rate lt 360 rad(Si)/h
- 1 reference 10 samples
- 5 biased
- 5 not biased (all IOs connected together to GND)
26Qualifying VASP
- Qualification according to ESCC Generic
Specification No. 9000 (6/6) - Chart 6 - Flow Chart for Radiation (SEE)
Qualification and Lot Acceptance Testing
ESA will give access to one of their SEE
radiation test facilities (HIF in Belgium
preferably, or RADEF in Finland). SEU test will
allow to characterize the behavior with and
without hardening. The latchup immunity of VASP
shall be tested up to a LET of 70 MeV/mg/cm² (use
37 tilt with Xenon) .
27Analog intellectual property reusability
- Such partnership is based on the unavoidable
sharing of know-how - video signal processing for space application
- radiation hardening from architecture down to
basic cells - high performances analog and mixed design (analog
front-end, 16 bits ADC, complex digital) -
- but shall protect the intellectual property of
each contributor. The main critical points are - Find a good balance in know-how sharing win-win
approach - Design result remains the CHIPIDEAs intellectual
property or need specific contract negotiation - Accommodate the difference in business models
between leader for Satellite Systems and a
world's leading analog/mixed-signal intellectual
property provider - Efficient reusability for analog blocks requires
- the stability in technology choice. A versatile
and perennial 0.35µm CMOS as XFAB XH035 appears
to be able to cover larger requirements than
VASP, thanks to the available options 5V
compatibility, RAM, high voltage. - Design Kit availability, configuration and
stability - a long term access to IP blocks
28End
- Thank you for your attention
- See you at AMICSA 2010 with test results
Philippe AYZAC THALES ALENIA SPACE philippe.ayza
c_at_thalesaleniaspace.com Jorge GUILHERME MIPS /
CHIPIDEA guilherm_at_chipidea.mips.com