IMAPS Global Business Council Roadmap Process - PowerPoint PPT Presentation


PPT – IMAPS Global Business Council Roadmap Process PowerPoint presentation | free to download - id: 3bf57-NjZiZ


The Adobe Flash plugin is needed to view this content

Get the plugin now

View by Category
About This Presentation

IMAPS Global Business Council Roadmap Process


... Industry Association (ESIA), the Japan Electronics and Information Technology ... obtaining consensus on industry drivers, requirements, and technology timelines. ... – PowerPoint PPT presentation

Number of Views:104
Avg rating:3.0/5.0
Slides: 55
Provided by: laurie96
Learn more at:


Write a Comment
User Comments (0)
Transcript and Presenter's Notes

Title: IMAPS Global Business Council Roadmap Process

IMAPS Global Business Council Roadmap Process
  • The Road Ahead

The GBC Roadmap Team
  • This Roadmap Process presentation was prepared by
    these members of the IMAPS Global Business
    Council National Technology Council
  • Steve Adamson (
  • Justin Blount (
  • Laurie Roth (
  • Lee Smith (
  • Andy Strandjord (
  • Jie Xue (

  • Where does IMAPS fit in with the ITRS and iNEMI
  • What is the ITRS Roadmap and how does it work?
  • What is the iNEMI Roadmap and how does it work?
  • How does IMAPS interact with this Roadmap
  • Why IMAPS should be involved.
  • IMAPS Areas of Focus.
  • If you are already familiar with the ITRS iNEMI
    Roadmap Process, skip to slide 19
  • The Roadmaps
  • ITRS
  • iNEMI
  • Summary IMAPS Areas of Focus.

ITRS iNEMI Packaging Roadmaps Intersect
IMAPS addresses the Semiconductor Packaging needs
of this space.
What is the ITRS?
  • The International Technology Roadmap for
    Semiconductors (ITRS) is an assessment of
    semiconductor technology requirements.
  • The objective of the ITRS is to ensure
    advancements in the performance of integrated
  • This assessment, called roadmapping, is a
    cooperative effort of global industry
    manufacturers and suppliers, government
    organizations, consortia, and universities.
  • The ITRS identifies the technological challenges
    and needs facing the semiconductor industry over
    the next 15 years.
  • It is sponsored by the European Semiconductor
    Industry Association (ESIA), the Japan
    Electronics and Information Technology Industries
    Association (JEITA), the Korean Semiconductor
    Industry Association (KSIA), the Semiconductor
    Industry Association (SIA), and Taiwan
    Semiconductor Industry Association (TSIA).
  • SEMATECH is the global communication center for
    this activity. The ITRS team at SEMATECH also
    coordinates the USA region events.

ITRS Technology Working Groups
  • The ITRS process encourages discussion and debate
    throughout the community about the requirements
    for success.
  • The key factor in the success of the Roadmap is
    obtaining consensus on industry drivers,
    requirements, and technology timelines.
  • The Technology Working Groups are the
    organizations that "build" the roadmaps.
  • These representatives assess the state of
    technology and identify areas that may provide
  • The TWG members also indicate opportunities for
    new research and innovation.
  • These groups are made up of volunteer technology
    experts from chip manufactures, supplier
    companies, universities and academia, technology
    labs, and semiconductor technology consortia.
  • The Technology Working Groups, also known as
    TWGs, are comprised of the technical disciplines
  • System Drivers
  • Design
  • Test and Test Equipment
  • Process Integration, Devices, and Structures
  • RF and Analog/Mixed-signal Technologies for
    Wireless Communications
  • Emerging Research Devices and Materials
  • Front End Processes
  • Lithography
  • Interconnect
  • Factory Integration
  • Assembly and Packaging This is the area where
    IMAPS will focus.
  • Environment, Safety, and Health

Example of ITRS Short Term Challenges
iNEMI has strong industry support.
iNEMI Roadmap Methodology
  • iNEMI focusses on top level industry segments via
    their Product Emulator Groups.
  • In addition, they address technology areas via
    their different Technology Working Groups.
  • A cross-cut matrix ensures feedback between the
    various groups.

iNEMI Technology Working Groups
  • Business Processes/Technologies
  • Product Lifecycle Information Management
  • Design Technologies
  • Environmentally Conscious Electronics
  • Modeling, Simulation Design Tools
  • Thermal Management
  • Manufacturing Technologies
  • Board Assembly
  • Test, Inspection Measurement
  • Final Assembly
  • Component Subsystem Technologies
  • Passive Components
  • RF Components Subsystems
  • Packaging This is one of the areas where IMAPS
    will focus.
  • Semiconductor Technology
  • Organic Substrates
  • Mass Data Storage
  • Connectors
  • Energy Storage Systems

iNEMI Cross-cut Matrix
A cross-cut matrix ensures feedback between the
various groups.
Example of iNEMI short term challenges
Update calendar for ITRS / iNEMI
  • 2006 ITRS Roadmap release scheduled for December
    4, 2006.
  • 2007 iNEMI Roadmap release scheduled for February
    2007 at APEX, Los Angeles.

Why IMAPS should be involved.
  • ITRS focuses mainly on front end wafer fab
    areas, with a chapter on Semiconductor Assembly
  • iNEMI focuses mainly on board level assembly,
    with a chapter on Semiconductor Assembly
  • ITRS/iNEMI are working together to align their
    Semiconductor Assembly Packaging Roadmaps.
  • Many of the same people are on both teams.
  • Some IMAPS members are also on both teams.
  • IMAPS focus is on Semiconductor Assembly
  • Its a natural fit to take the output of the
    ITRS/iNEMI Semiconductor Assembly Packaging
    Roadmaps and use that output to direct IMAPS
    activities towards solving gaps in the roadmap.
  • IMAPS corporate members will benefit by
    developing real industry solutions for real
    industry challenges.

Global Semiconductor Packaging Materials Outlook
Market Size for Materials Market Opportunities
for IMAPS members.
Source SEMI Industry Research and Statistics and
TechSearch International, November 2005
This forecast was supplied courtesy of SEMI
Techsearch International. The full report is
available from SEMIs web catalog at
Launched The Road Ahead in Advancing
Microelectronics 4/06
Roll-out plan for IMAPS to address roadmaps
  • Form a GBC Roadmap Team.- DONE
  • GBC Roadmap Team creates a roadmap template (red
    brick) and identifies current gaps on the
    existing roadmaps. - DONE
  • GBC Roadmap Team communicates those gaps to the
  • GBC and NTC structure future IMAPS events to
    focus on those gaps ongoing.
  • Dave Saums to give short presentation at LED
    Thermal ATWs in September 2006.
  • Meantime, GBC/NTC to support ITRS/iNEMI updates
    with input communicate back to IMAPS
  • Use IMAPS members on the ITRS/iNEMI roadmap TWGs
    to facilitate communication Laurie Roth, Howard
    Imhof....and other volunteers.

Recommended Areas of Focus for IMAPS Members
  • Develop Feasible Embedded Components.
  • Develop Enhanced Materials to Enable Wafer Level
  • Bring Solutions to Resolve Thermal Management
  • Develop New Materials to Reduce System Cost While
    Delivering the Necessary Performance.
  • Close the Gap Between Chip and Substrate
    Interconnect Density.
  • Resolve the issues low K and Cu bring to

The Roadmaps
The complete chapter can be downloaded from the
ITRS website http//
AP2005.pdf The following slides contain key
ITRS 2005 Semiconductor Packaging Roadmap Table
of Contents
All of these topics and those on the next slide
are comprehensively covered in the ITRS
Roadmap. This presentation will focus on the key
challenges only.
  • Packaging Materials Requirements
  • New Materials
  • Embedded and Integrated Passives
  • Assembly and Packaging Infrastructure Challenges
  • Electrical Design Requirements
  • Cross Talk
  • Power Distribution and Power Subsystem
  • Thermo-mechanical Challenges in Electronic
  • Mechanical Challenges
  • Mechanical Modeling and Simulation and Validation
  • Thermal Modeling and Simulation and Validation
  • Equipment Requirements for Emerging Package Types
  • Potential Solutions
  • Wafer Level Packaging
  • Chip to Next Level Interconnect
  • Package to Board Interconnect
  • Fine Pitch Ball Grid Array/CSP Packages
  • Socketed Parts
  • Embedded and Integrated Passives
  • Chapter Scope
  • Difficult Challenges
  • Technology Requirements
  • Single Chip Packages
  • High Pin-Count Packages
  • Wafer Level Packaging
  • System in a Package (Multi-chip Packages, 3D
  • Flexible Substrates and Interconnect
  • Optoelectronic Packaging
  • RF Packaging
  • MEMS
  • Medical and Bio Chip Packaging
  • Biocompatibility
  • Bio Packaging Reliability
  • Integrated Circuit
  • Manufacturing
  • Cost
  • Reliability
  • Package and Interconnect Characterization and

ITRS 2005 Semiconductor Packaging Roadmap Table
of Contents continued
  • System in Package (SiP) System Level
  • Types/Categories of SiPs
  • Side by Side Placement (Horizontal Packages)
  • Stacked Structures
  • Package-on-Package (POP), Package-in-Package
  • Stacked Die Packages
  • Chip to Chip/Wafer Structure
  • Embedded Structures
  • Technologies for SiP
  • Wafer level SiP and 3 D Integration Technologies
  • Technologies for Embedded Devices
  • Challenges for SiP
  • Thermal management
  • System in Package Outlook
  • Wafer Thinning
  • Glossary of Terms
  • Cross-Cut ITWG Issues
  • Design
  • Factory Integration

ITRS Single Chip Package
  • Incremental improvements in traditional assembly
    technologies will not be sufficient to meet
    market requirements.
  • The substrate dominates the cost of single chip
  • Cost per pin has been trending up, instead of
  • Operating temperatures are a problem in harsh
  • Higher frequency chip-to-board speeds for
    peripheral buses.

ITRS High Pin-Count Packages
  • Package pin count grows as higher frequency and
    higher power density demand more power and ground
  • Substrate technology requires micro-vias, blind
    buried vias, stacked vias and tighter lines and
  • Substrate technology advances lead to significant
    cost increases for design/test and a reduced
    supplier base.
  • System-in-Package will become more important to
    reduce the need for high density interconnects in
    the package substrate and the PCB.

ITRS Chip-to-Package Substrate
Development work is required for finer pitch
in-line wire bond area array flip chip.
ITRS Package Substrate Physical Properties
Near Term
ITRS Package Substrate Physical Properties
Long Term
ITRS System-in-Package - definitions
  • SiP enables reduction in size, weight, cost
  • System-on-Chip can address size, weight power,
    but at cost, design test premiums.
  • SiP integrates multiple functions/devices in a
    single package.
  • Can integrate different elements such as MEMS,
    opto, bio....
  • Includes 3D stacked die packaging.
  • Requires Known Good Die.

ITRS System-in-Package Requirements
The number of stacked die and the number of die
in a SiP are challenges.
ITRS Thinned Wafers
Long term challenge for extreme thin packages.
ITRS Wafer Level Packaging
  • Near term challenges
  • I/O pitch between 150 µm - 250 µm gt100 I/O
  • Solder joint reliability
  • Wafer thinning and handling technologies
  • Compact ESD structures
  • TCE mismatch compensation for large die

ITRS Flexible Substrates
  • Near term challenges
  • Conformal low cost organic substrates
  • Small and thin die assembly
  • Handling in low cost operation

ITRS Interconnect
It is very challenging to maintain packaging
reliability with strong chip-to-package
interaction resulting from new materials, new
processes, and new interconnect features at the
Si level.
ITRS Interconnect (contd)
ITRS Optoelectronic Packaging
  • Package Sealing
  • Hermetic sealing to protect the optical devices -
    TO header butterfly packaging.
  • Non-hermetically sealed organic packaging for
    cost sensitive applications.
  • Alignment
  • lt 0.5 µm alignment between single mode fiber
    optical device for high data rate applications.
  • 5 to 10 µm alignment accuracy for cost sensitive
    applications, using relatively large diameter
    polymer optical fiber (POF)
  • Adhesive to assure alignment through succeeding
    high temperature processes product usage life.
  • Materials
  • POF material improvement in attenuation reduction
    and data rate increase is required.
  • Material development for poly-clad-silica (PCS)
  • Optically clear molding compound or clear glob
    tops for optical windows.
  • Vertical integration to include more
    functionality in a package.
  • Wafer-level-packaging (WLP) process to integrate
    lenses or other micro-opticalelectro-mechanical
    system (MOEMS) devices, and to provide
    environmental protection for a VCSEL wafer.
  • Some micro-optical components, e.g. polymer
    waveguides and beam reflectors, may be embedded
    in the SiP substrate.
  • A BGA based SiP may house optical connectors,
    laser diodes, photodetectors, CMOS IC containing
    receivers/drivers and multiplexer/demultiplexer,
    plus RF connectors, and decoupling capacitors.

ITRS RF Packaging
  • Many of the technology challenges for RF
    packaging arise from the fact that the IC
    packaging engineering practice, technology
    knowledge base, and manufacturing infrastructures
    have been based upon digital IC packaging
    developed in the last forty odd years.
  • Issues
  • The inductance characteristics associated with
    bonding wires and leaded packages, and effect of
    molding compound materials limit the RF
  • RF package modeling tools and materials
    properties database for package design and
    device-package co-design for the broad spectrum
    of RF market applications.
  • Improvements in materials propertiesmolding
    compounds, underfills, substrates are required.
  • Being able to embed passive components in LTCC.
  • To meet the low cost challenges, embedded
    inductance and capacitance components and
    networks in organic packaging for RF applications
    must be diligently pursued.
  • Tools to enable device package co-design in SIP
    packages will be very important.

ITRS Medical Bio Chip Packaging
  • No interaction with body tissues and fluids.
  • No inflammatory reactions.
  • No toxicity to bio-organisms.
  • No outgassing or other decay products that may be
    harmful to bio-organisms.
  • Must be chemically inert to various
    concentrations of bio-reagents including ethanol.
  • May include high flow rates with significant back
  • Major concerns are patient safety and risk
  • For life-sustaining devices, component failure
    rate as low as 100 ppm, few ppm critical failure
  • Challenge to capture low occurrence failures in
    reliability testing.
  • EMI is a major concern.
  • Pressure requirements in a barometric pressure
    chamber or while scuba diving.
  • Defibrillation devices could generate significant
    localized heating in the high voltage charging
    circuit when delivering therapy, challenging the
    package substrate and PCB.
  • In accordance with regulatory requirements for
    medical devices
  • Requirements for control of the manufacturing
    environment, labeling of the packages, and

  • Today packaging costs often exceed die
    fabrication costs.
  • Leadfree solders.
  • Low K High K dielectrics.
  • Higher processing temperatures.
  • Wider range of environmental temperatures.
  • More efficient thermal management needed.

ITRS Reliability Simulation
New failure modes caused by new materials needed
to meet environmental and performance
requirements, result in significant challenges in
field reliability prediction based on accelerated
lab testing for broad product application field
  • The introduction of the new materials and
    structures to meet environmental, heat and speed
    requirements are posing new reliability
  • New technology will be required to meet the
    reliability goals including
  • New reliability tests such as drop tests for
    mobile products.
  • Correlation between field- and laboratory
  • Improved methods for failure detection and
    analysis (e.g., X-ray, acoustic, nano-deformation
    and localized residual stress measurement.)
  • Materials and interface characterization.
    Interfacial delamination will continue to be a
    critical reliability hazard that is worsened by
    the trends to larger chips, new materials and
    increased layer count. More layers require the
    understanding of more interfaces.
  • Simulation and modeling for life time prediction
    (e.g., multi-field coupling, structure-property
    correlation, ab-initio methods, modular and
    parametric approaches).

ITRS Packaging Materials
ITRS Infrastructure
  • Electrical design
  • Cross talk
  • Power distribution power subsystem
  • Thermo-mechanical
  • Modeling Simulation
  • Equipment

  • The iNEMI Roadmap is only available for download
    to TWG members or on-line purchase.
  • The following slides contain key excerpts from
    the 2007 Roadmap Update-in-progess.

(No Transcript)
(No Transcript)
(No Transcript)
(No Transcript)
Recommended Areas of Focus for IMAPS
Members Summary
  • Develop Feasible Embedded Components.
  • Develop Enhanced Materials to Enable Wafer Level
  • Bring Solutions to Resolve Thermal Management
  • Develop New Materials to Reduce System Cost While
    Delivering the Necessary Performance.
  • Close the Gap Between Chip and Substrate
    Interconnect Density.
  • Resolve the issues low K and Cu bring to

Back Up
ITRS Difficult Challenges 32 nm Near Term
The ITRS Roadmap segments issues into those that
are Near Term affect Wafer Nodes 32 nm and
those that are Long Term affect Wafer Nodes lt32
ITRS Difficult Challenges 32 nm Near Term
ITRS Difficult Challenges 32 nm Near Term
ITRS Difficult Challenges 32 nm Near Term
ITRS Difficult Challenges lt 32 nm Long Term