Performance Modeling of RuleBased Architectures as DiscreteTime Quasi BirthDeath Processes - PowerPoint PPT Presentation

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Performance Modeling of RuleBased Architectures as DiscreteTime Quasi BirthDeath Processes

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Title: Performance Modeling of RuleBased Architectures as DiscreteTime Quasi BirthDeath Processes


1
Performance Modeling of Rule-Based Architectures
as Discrete-Time Quasi Birth-Death Processes
  • Authors
  • Sándor Palugyai, Máté J. Csorba
  • Ericsson Hungary, Test Competence Center
  • http//ttcn.ericsson.se/
  • E-mail sandor.palugyai, mate.csorba_at_ericsson.co
    m

2
Motivation
  • Rule-based architectures
  • e.g. a firewall system in a router
  • Design a mathematical model
  • reproducability
  • Predict performance parameters
  • packet delay
  • packet loss
  • etc.

3
Introduction
  • Introduction to Rule-based architectures (Access
    Control Lists)
  • Introduction of interfaces
  • Markovian theory (QBDs)
  • Our model (structure, mathematical background)
  • Accuracy, results, future plans

4
Rule-based architectures
  • Access Control Lists
  • Firewall systems
  • Database applications
  • Alternative behavior in software architectures
  • TTCN-3 alt construction
  • Switch Case

5
Example Access Control Lists
  • Network protection and admission control
    mechanisms provided by Access Control Lists
  • Impact on performance based on linear execution
  • Significant packet-delay and loss might appear

6
ACLs applied
  • Permit or deny network segments and individual
    hosts
  • Sequential execution
  • access-list 111 permit tcp any host 10.120.23.1
  • access-list 111 deny any 10.120.23.0 0.0.0.255

7
Introduction of interfaces
  • Systems with a single processor and bus
  • Interrupted packet processing
  • Input may interrupt output packet handling too

8
Quasi Birth-Death processes
  • N(t) level process, J(t) phase process
  • QBD ( one level up or down, or inside the actual
    level )
  • P transition probability matrix ( A matrices )

9
Derivation of performance indices from the model
  • Balance of the embedded chain
  • Queue length distributions
  • Delay !
  • Packet loss !
  • Output traffic of the Models

10
Features of the Interface model
  • Can model the delay caused by the input/output
    interfaces (where queuing might appear)
  • modeling of Hardware elements
  • Rules can be accept (fwd.) or deny (drop)

11
QBD structure of the Interface model
12
Matrix-structure of the Interface model
13
Matrices of the Interface model
14
Derivation of performance parameters
15
Accuracy of the Interface model
16
Properties of the Interface model
  • The model of list-structures with interfaces
  • Deduction of the Interface model
  • Tool for evaluation of the model (parametrical)
  • Simulations and measurements (ns-2)
  • Applicable for other list topologies

17
Future work
  • Proofs of other conjectures
  • Closing the gaps
  • Model more hardware related structures

18
  • Thank You for Your Attention!
  • E-mail sandor.palugyai, mate.csorba_at_ericsson.co
    m

19
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