Herschel PACS Instrument Hardware Design Review IHDR SIGNAL PROCESSING UNIT SPU HW Unit, Startup SW

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Herschel PACSInstrument Hardware Design Review
(IHDR) SIGNAL PROCESSING UNIT(SPU)HW Unit,
Start-up SW and Low-level SW Drivers

• J. Cepa, J.M. Herreros
• INSTITUTO DE ASTROFÍSICA DE CANARIAS (IAC)

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CONTENTS

• Progress made since IBDR
• HW and SW DD Performance Status
• PA/QA Status
• Critical Areas
• CRISA Contracts/Management Status
• Documentation Status List
• Financial Status
• Schedule Status

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PACS SPU AVM BOX OUTLINE EVOLUTION
IBDR CONFIGURATION (EM AVM Models)
IHDR CONFIGURATION (AVM Model)
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PACS SPU FM BOX OUTLINE EVOLUTION
IBDR CONFIGURATION
IHDR CONFIGURATION
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PACS SPU / LFI REBA QM BOX OUTLINE
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PACS SPU FM BOX OUTLINE
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SPU SWL LWL CPU Board.DSP Side. EM AVM Models
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SPU SWL LWL CPU Board. SMCS Side. EM AVM
Models
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Data Acquisition and DC/DC Converter Board. EM
Model
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Data Acquisition and DC/DC Converter Board. AVM
Model
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SPU UNIT BUDGETS EVOLUTION
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PROBLEMS ENCOUNTERED SOLUTIONS ADOPTED

• SPU-LWL AVM EEPROM contents corruption.
• The fail was investigated and no problem was
  found in the design. The EEPROM device that
  failed was replaced by another one and the
  verification program was executed around fifty
  times, no failure appeared neither in LWL nor in
  SWL board.
• SPU AVM Conducted Emissions test results.
• In the frequency domain and differential mode,
  some out-of-limits were identified in the ranges
  30KHz to 1MHz and 1MHz to 30MHz. In common mode
  the results are inside limits.
• The results are inside limits for emissions in
  time domain as well as for inrush current
  requirements.
• To overcome the situation the design has been
  improved. Nevertheless the PCB, the packaging and
  the grounding was not totally FM representative.
  It is expected to be inside specifications for
  the QM and FM.

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PROBLEMS ENCOUNTERED SOLUTIONS ADOPTED

• SPU EM EEPROM Loading Problem.
• An HW problem identified some time ago needs to
  be repaired asap. It has been requested to MPE to
  send the unit to CRISA.
• ASICs Problem
• See MPRs.

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HW AND SW DD PERFORMANCE STATUS

• System engineering HW electrical design
• System performances optimisation
• ASIC PSC re-engineering has been completed,
  nevertheless this delta activity has introduced a
  delay in the schedule.
• CPU PCB re-design to fully maximise the critical
  performances margins has been completed.
• Other modules PCBs design update status
• Mother Board design finished.
• DAUCV PCB design finished.

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HW AND SW DD PERFORMANCE STATUS

• Flight SW Engineering
• Unit tests Report ? Finished
• Code inspection metrics Report ? Finished
• Budgets Report ? Finished
• DDD ? Finished
• SW ICD ? Finished
• SW drivers Validation ? Finished
• SPU SUSW Validation ? Finished
• Users Manual (SW part) ? Scheduled for mid of
  November

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HW AND SW DD PERFORMANCE STATUS

• ASIC development / Validation integration with
  System / CPU
• Next step consisting on the critical
  characterisation / validation of the final PSC
  ASIC design in its -E type version, installed
  on a reference CPU model manufactured on a
  Printca PCB version for flight, seeking the
  maximum degree of representativity with the QM
  and FM HW.
• This activity is scheduled in December 2003 /
  January 2004.

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HW AND SW DD PERFORMANCE STATUS

• Physical Engineering
• Mechanical analysis ? Finished
• Thermal analysis ? Finished
• Verification Engineering
• Going on with the generation of the final edition
  of a Verification Control Document and the
  Equipment Qualification and Acceptance Test Plan
  (functional and electrical part).
• VCD Issue 3 draft1 available.

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HW AND SW DD PERFORMANCE STATUS

• Procurement Parts Engineering
• Results from testing with CPU has derived in the
  need of very limited additional procurement. New
  parts has been compiled and transmitted to
  Tecnologica for urgent ATPs placement.
• Revision of the procurement status of passive
  parts for QM by Crisa is under way.
• Magnetics procurement for QM and Flight models
  has been initiated.
• New version of ASIC PSC has been negotiated and
  re-procurement has been launched.

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HW AND SW DD PERFORMANCE STATUS

• MAI activities
• SPU AVM has been refurbished and sent to MPE to
  meet system integration needs.
• Tests activities
• SW delta Integration ? Finished
• SW Unit Tests ? Finished
• SW Validation ? Finished
• ASIC/CPU System Integration/Validation and
  characterisation ? Finished with prototype HW
• Delta System Integration/Validation and
  characterisation on final ASIC/CPU version ? Not
  started
• Equipment Boards verification at MAI ? Not
  started
• Equipment Qualification testing ? Not started

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PA/QA STATUS

• PA MANAGEMENT
• Critical Items List waiting for the availability
  of the functional FMECA which is ready and in its
  visa cycle.
• MATERIALS AND PROCESSES SELECTION AND CONTROL
• No news wrt the delivered documentation.
• EEE PARTS SELECTION AND CONTROL
• Parts availability and dates from TLG to be
  checked.
• PSC-ASICs purchase order for QM and flight placed
  on beginning October 2003.
• CLEANLINESS AND CONTAMINATION CONTROL
• No news wrt the delivered documentation..

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PA/QA STATUS

• RELIABILITY ASSURANCE
• Functional FMECA in its way out. Detailed I/F
  FMECA HW/SW Interaction analysis, PSA and WCA
  summary confection under way.
• QUALITY ASSURANCE
• A final VCD is under generation, first draft
  available for revision. Test Plan underway
  according to current VCD status. Test Procedures
  pendant. QM TRR foreseen beginning March 04, TRB
  beginning June 2004.
• SOFTWARE QUALITY ASSURANCE
• Refer to SW engineering.
• CONFIGURATION MANAGEMENT CONTROL
• No news wrt the delivered documentation.

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CRITICAL AREAS

• NONE IDENTIFIED.

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CRISA CONTRACTS/MANAGEMENT STATUS

• PHASE I EM Model. HW Unit, Start-up SW and
  Low-level SW Drivers DD and MAIT? Finished
• PHASE II AVM Model. HW Unit, Start-up SW and
  Low-level SW Drivers DD and MAIT ? Finished
• PHASE III QM Model. HW Unit, Start-up SW and
  Low-level SW Drivers DD, MAIT and Flight
  Qualification ? In progress.
• PHASE IV-A QM FM HW procurement of ASICs, PCBs
  and Magnetics ? Activities and contract in
  progress.
• PHASE IV-B FM MAIT and Qualification ? Not
  started.

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DOCUMENTATION STATUS LIST

• Pending documentation is almost ready planned to
  be available end/beginning 2003/2004.
• For details see MPRs.

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FINANCIAL STATUS

• Delta funds will be requested before end 2003 to
  cover Phase IV-B.

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SCHEDULE STATUS

• LFI REBA / PACS SPU QM delivered mid 2004.
• Estimated PACS SPU FM delivered to MPE Q3 2004.
• Detailed schedule is under elaboration.