DefectDesign Learning from Electrical Test

1
Defect/Design Learning fromElectrical Test

• Dr. Bernd Koenemann
• David Abercrombie
• Mentor Graphics Corporation

2
About This Tutorial

• Three sections 50 mins each
• 10 min breaks between each section
• Speakers
• David Abercrombie
• DFM Program Manager at Mentor Graphics
• Bernd Koenemann
• DFT Chief Scientist at Mentor Graphics

3
Agenda

• Part I
• Introduction
• Yield Challenges in nm Technology
• Design for Manufacturing
• Part II
• Defect Learning
• Yield Learning with Test
• Part III
• Emerging Methodologies
• Summary Discussion

4
Agenda

• Part I
• Introduction
• Yield Challenges in nm Technology
• Design for Manufacturing
• Part II
• Defect Learning
• Yield Learning with Test
• Part III
• Emerging Methodologies
• Summary

5
There is a Problem!
rumors are running rampant that Broadcom,
Nvidia, and other TSMC customers are unhappy with
the company's 0.13-micron chip yields
Silicon Strategies 12/29/2002 "I believe the
issue with 0.13-micron is the combination of the
design and process"
6
DFM Related Yield Loss
Lower Mature Yields
Slower and UnstableYield Ramps
Lower Initial Yields
7
Design Re-Spins
Source Mark Miller, eeDesign.com, 2004
8
Business Impact of DFM Yield Loss
Yield ()
Production
9
What is IC Yield?
10
Yield vs Defect Density
Defect Density Yield (Small) Yield
(Large) 0.015625 D/cm2 99.9 96.9 0.03125
D/cm2 99.8 93.9 0.0625 D/cm2 99.7 88.2 0.1
25 D/cm2 99.3 77.9 0.25 D/cm2 98.6 60.7 0.
5 D/cm2 97.2 36.8 1 D/cm2 94.6 13.5 2D/cm2
89.4 1.8
11
Yield Models
12
Do the Models Work?
13
What is the Problem?
Design 2
Design 1

• Same Die Size
• Same Complexity
• Same Foundry
• Same Process

14
What is the Problem?
Design 1
Design 2
42 Yield
77 Yield
Interactions Between Design and Manufacturing
15
What is Changing?
Source Graph, International Business Strategies,
Inc
16
What are Random Defects?
Source PDF Solutions - Website
17
Dont The Fabs Improve Defectivity?
Continuous 50 Area and Defect Density Reduction
Per Node
18
What are Systematic Defects?
Source Madge, et.al., 2004
19
What Has Systematically Changed?
Source Gupta, Wescon 2005
20
Wont OPC Save the Day?
Source Gupta, Wescon 2005
Source Rieger, et. al., DAC 2001
21
What Are Parametric Defects?
WorstCaseSpec
StatisticalSpec
EDAModel
Probability
Parameter
22
Transistor Variation
Sources Drennen, Wescon, 2005 Borkar et al.,
GVLSI 2002
23
Interconnect Variation
Resistive Vias
CMP Dishing Erosion
Multilayer Topography
Profile Variation
Sources Madge, klabs.org., 2000 Gupta, Wescon,
2005 Fisher, Semi Intl., 2005
24
Environmental Variation

• Varies spatially and with time (switching
  activity)

From C. Visweswariah, IBM
25
The Problems are Harder to Find
X Lot1 O Lot2
Source Madge, et. al., 2004
26
Why Doesnt Someone Fix It?
Integrated Device Manufacturer
Semiconductor Industry Disaggregating
27
What is DFM?

• Design for Marketing
• Destined for Mayhem
• Design for Mfg (Yield)
• Design for Money

28
I Thought Yield Was a Fab Job?
29
DFM DF(x)

• DFY (Design for Yield) Catastrophic Failures
• Random or Systematic Short or Open
• DFV (Design for Variability) Variation Failures
• Parametric Variation (?R, ?C, ?L, ?W, ?T, ?P)
• DFR (Design for Reliability) Delayed Failures
• Electromigration, HCI, GOI, etc.
• DFT (Design for Test) Missed Failures
• Test Escapes (DPM)
• DFD (Design for Diagnostics) Learned Failures
• Failure Analysis

30
DFM is a Process
Update Design Practicesand Mfg Processes
31
DFM is a Flow
32
DFM Analysis Techniques

• Critical Area Analysis
• Layout Sensitivity toRandom Defects

• Recommended RuleAnalysis
• Adherence to StricterDesign Rules

Sources Predictions Software, Website Mentor
Graphics
33
DFM Analysis Techniques

• Litho Simulation
• Layout Sensitivity toLithographic Variation

• CMP Simulation
• Layout Sensitivity toPolish Variation

Sources Brion, Website Xyalis, Website
34
DFM Enhancement Techniques
Sources Predictions Software, Website Liebmann,
IBM
35
DFM Enhancement Techniques
Area
Dd
Dd Perf

• Cell Swapping
• Trade Cells forYield

• Metal Fill
• Add Extra Shapes tomake more uniformpolish
  thickness

Sources Strojwas, Wescon 2005 Gupta, Wescon
2005
36
DFM Identification Techniques

• Design for Test Techniques
• Fab Inspection and Metrology
• Yield Management Systems
• Test Chip Characterization
• Memory Bitmapping
• Logic Scan Diagnostics
• Logic Bitmapping
• Failure Analysis

Part II of this tutorial will focus on these
topics
37
Different Views on Yield

• Mfg Yield Care Abouts
• Failure Location?
• Failure Mode?
• Process Step?
• Rate per Tool?
• Process Conditions?
• Tool Conditions?
• Chemical Make-up?
• Shape and Color?

• Design Yield Care Abouts
• Failure Feature?
• Failure Rate?
• Mask Layer?
• Rate per Design Dimension?
• Layout Conditions?
• Layout Alternatives?

38
Part II
39
Agenda

• Part I
• Introduction
• Yield Challenges in nm Technology
• Design for Manufacturing
• Part II
• Defect Learning
• Yield Learning with Test
• Part III
• Emerging Methodologies
• Summary

40
The New Role of Test

• Test may be the first real opportunity to uncover
  the statistical impact of new catastrophic and
  parametric defect sources
• Test can become a key tool for statistical design
  verification and design/yield learning

41
Adaptation of Test
Realistic
Wafer/chips
Faults
Test
ATPG/Fault-Grading
Low Cost
ShippedProducts
TestFails
42
Parametric Constraints Timing

• Have to deal with defects and process variability
• Test edge placement limited by tester accuracy

Conceptual Arrival Time and Defect Distribution
for a Delay Path
f(d)
Requ. Arrival Time
d
nom.
1
2
-1
-2
43
At-Speed Test With On-Chip PLL

• ATE controlled scan loading (i.e. slow shift)
• On-chip PLL controlled launch capture

44
Targeted Detection

• E.g., defect-based approach
• Note may skip circuit simulation for some fault
  types

45
Auxiliary Coverage Metrics

• Relate detection to some test set properties
• E.g., n-detect profile of stuck-at tests

35
Individual
100
Fallout
30
91
25
Cumulative Fallout Ratio
59
76
20
Failed Devices
15
10
5
0
2nd Detect
3rd Detect
4th Detect
5th Detect
Pattern Set
From B.Benware et al., LSI Logic, Mentor Graphics
46
Low Cost Scan Test Compression

• High Test Quality
• No loss in test coverage compared to normal scan
• Support for all fault/pattern types
• Stuck-at, transition, path delay,
  multiple-detect, IDDQ, bridging, etc.
• Combinational, sequential, multi-load, etc.
• Compression of test time and/or test data volume
• Low overhead (gate count, placement/wiring,
  power, timing, etc.)
• Minimal impact to functional logic design
• Minimal performance impact

47
On-Chip Test Compression

• Uses ATPG
• X-state handling
• Change design
• Masking
• X-tolerant compaction
• Diagnostics
• Bypass mode
• Direct diagnostics (no bypass needed)

Decompressor
Compactor
Chip
CompressedStimuli
CompactedResponses
ATE
48
Defect Learning

• Background
• Inspection/metrology
• Test/characterization Vehicles
• Yield management systems
• Enhanced learning with test
• Debug/diagnostics/failure-analysis
• Statistical processing

49
Inspection/Metrology

• Scanning for visible defects (mask/wafer)
• Special equipment
• Creates defect maps
• Measurement/tracking of process parameters
• Metrology equipment for specific process issues
  (e.g., surface planarity, oxide thickness, etc.)
• Equipment logs
• Measurement of circuit parameters
• Scribe-line (KERF) monitors
• Dedicated monitor structures
• On-chip monitors (e.g., PSRO, etc.)

50
In-Line Inspection (Surface Scan)
Equipment
Results File
e.g., Defect x-y-coordinates Defect size Defect
classification Etc.
Detailed Image
Wafer Map Image
From Multiple Sources
51
In-Line Inspection Characteristics

• Visualizes defects
• Defect densities
• Spatial distributions
• Time-consuming
• Limited subset of wafers/layers/process steps
• No immediate indication of yield impact if defect
  density is within expectations
• Limited scope
• Not all defects are visible
• Significance of non-visible defects is growing
  (ITRS)

52
Test Vehicles

• Simple monitor structures for specific defect
  types
• E.g., metallization, vias, contacts, etc.
• Sophisticated design/process characterization
  monitors
• E.g., multiple defect types, representative of
  design/library elements, etc.

53
Simple Test Structures

• Serpentine, Comb, Chain Structures

Serpentine From Hess, et al., 2001
54
Sophisticated Test Vehicles

• Combination of multiple monitor structures
• Targeting random and feature-based defects
• Integrated into comprehensive characterization
  flow

From PDF Solutions
55
Test Vehicle Characteristics

• Extract defect densities and yield sensitivities
• Multiple defect categories
• Representative circuit structures can reveal
  impact of defects on electrical fails
• Costly
• Dedicated designs that must be processed through
  line
• Design time, limited runs, etc.
• Limited scope
• Only detect/measure defect rates related to the
  circuit structures provided in the test vehicle
• May or may not include all yield-sensitive
  features found in real product designs

56
Yield Management Systems

• Infrastructure for monitoring and analyzing yield
  issues
• Data collection
• Data warehousing
• Data mining/analysis
• Increasingly comprehensive
• Many data types (e.g., logistics, equipment,
  metrology, binning, etc.)
• Many analysis routines (e.g., queries, report
  generation, visualization, alert automation,
  etc.)
• Customizable (e.g., database extensions,
  scripting/APIs, etc.)

57
Example E-Diagnostics Infrastructure
From Kot and Yedatore, Semi International, 2003
58
Example Visualization (Test)
Source, R. Madge, ITC 2004
59
Yield Management Systems Characteristics

• Very comprehensive
• Logistics, equipment, events, metrology, binning,
  etc.
• Can enable fast problem detection/correction
• Available and flexible
• Offered by multiple vendors
• Extendible data bases, queries, analyses,
  visualizations
• Limited scope
• May not have access to intra-chip design data
• Analysis resolution primarily at wafer-map level
• Extending resolution to intra-chip design/process
  interactions generally requires home-grown
  add-ons (happening in several places)

60
Diagnostics

• Finding the root-cause of a particular test fail
• Characterizing the failing behavior
• Localizing the most likely problem area
• Integral part of
• Silicon debug
• Failure analysis

61
Flow/Equipment/Tools for Silicon Debug
Production Tester and/or Validation System
Detect a Fault (Test, Fault Detection)
Engineering Tester, Temperature Control Unit
(TCU)
Characterize the Fault (Fault Characterization)
Engineering Tester, Prober, CAD Nav, TCU
Internally Isolate the Fault (Fault Isolation)
Simulation, Debug SW Tools, Engineering Tester,
Prober, TCU
Determine Design Flaw (Bug Identification or
Root Cause)
Simulation, Design Tools, FIB, CAD Nav, Prep
Tools
Fix the Bug (Engineering Change Order)
Verify the Fix (Design Verification)
FIB, CAD Nav, Prep Tools Design Verification Tools
From S. Maher
62
Example Equipment of the Trade
Source Credence/NPTest
63
Example Time-Resolved Backside Imaging
.13mm Inverter Chain Image . 2mm Image
Resolution (Through Si Backside)
Source Credence/NPTest
64
Memories

• Memories are relatively easy to diagnose
• Regular logic structures (word, bit)
• Regular physical structures (row, column)
• Bitmapping (i.e., logging the failing logic
  words/bits) is supported by Automatic Test
  Equipment (ATE) and Built-In Self-Test (BIST)
• Stand-alone and embedded memories in product
  chips have been and are important defect learning
  vehicles

65
Memory Diagnostics

• Log fail bitmaps from ATE/BIST
• Convert logical maps to physical maps
• Requires access to physical design structure
• Visualize/analyze logical/physical fail bit maps
• Look for characteristic patterns (e.g.,
  single-bit fail, row/column fail, etc.)
• Overlay with other data, e.g.,
• Layout (GDS II)
• Defect maps from in-line inspection
• Requires reticle/wafer map for coordinate
  translation
• Initiate Failure Analysis (FA)

66
Bit Mapping

• Use Case Flow

67
Bit Mapping
68
Physical Memory Fail Bitmap Examples
Vertical PairBit Line Contact
Partial ColumnResistive Bit Line Short
Multi-RowAddress Decoder
SwatchCMP Scratch
Entire BitSense amp, I/O
CatastrophicTiming Circuit
From R. Aitken, ARM/Artisan
69
Overlay of Bitmap and Defect Map
70
Logic

• Logic is more difficult to diagnose
• Non-regular
• Limited visibility of internal circuit states (no
  equivalent to direct bitmapping as for memories)
• Traditionally has been a time-consuming manual
  effort
• Significant automation possible for designs with
  scan
• Enhanced state visibility at scan cells and
  primary outputs
• However, still no direct mapping of logic outside
  scan cells
• Failing scan cells may not be actual problem
  locations

71
Example
From A. Weber, Semi International, 2004
72
Logic Diagnostics (with Scan)

• Log some number of fail sets (failing scan cells
  and primary outputs) from ATE or BIST
• Run logic fault isolation software
• Create gate-level callouts (net/pin names, fail
  type) most likely near the problem area
• Visualize callouts in layout
• Requires link between gate-level netlist and
  layout (e.g., from running LVS)
• Overlay callouts with defect maps or other
  information
• Requires translation to/from wafer-level
  coordinates
• Initiate Failure Analysis (FA)

73
Logic Mapping
Fail Net Visualization
74
Diagnostic Flow for FA
DesignDB
Netlist
FailSets
Run Test withFail DataCollection
Logic Fault Isolation
Determine Failing Net Location
Visualize Failing Net
IdentifyDie ofInterest
NavigatetoLocation
Determine Cause of Failure
75
Fault Localization Software
ATE/BIST
Fail sets
TestPatterns
Note Fault simulation can be run ahead of time
to pre-calculate a fault dictionaryor after the
fact during diagnostics
76
Callout Example
Note from IBM TestBench
77
Part III
78
Agenda

• Part I
• Introduction
• Yield Challenges in nm Technology
• Design for Manufacturing
• Part II
• Defect Learning
• Yield Learning with Test
• Part III
• Emerging Methodologies
• Summary

79
Statistical Fault Detection

• Within DieDeltas
• Between DieDeltas
• NeighborhoodBase Downgrades
• Location BasedDowngrades

Source Madge, et. al., Klabs.org
80
Statistical Diagnostics for Logic

• Emerging defect/yield learning method for complex
  logic designs
• Implement comprehensive fail set logging for
  initial ramp and for volume production test
• Run logic fault isolation on many/all fail sets
  (could be thousands per day)
• Write all callout information into database
• Statistically sort, analyze, and visualize the
  cumulative callout information, e.g.,
• Query by cell-type, cell-instance/location, etc.
• Stack results on chip layout, reticle, and/or
  wafer map
• Compare with yield predictions
• Etc.

81
Volume Scan Diagnostics
82
Design Feature Extraction
Feature Extraction
Prioritized Fault candidates
83
Inductive Fault Modeling
Test Aware Node
84
Using the Product as a Test Chip

• Test Chips
• LayoutSpecificStructures

• Product Die
• Layout CombinationalStructures

85
Data Generation
86
Correlation Example

87
Failure Rates
???
Unknown
88
Failure Probabilities
89
Physical Yield Analysis Flow
Netlist
Predict Net Yields
Calc Delta Between Predictions and Actuals
Calculate Fail Probabilities
SCAN Test Data
Run SCAN Test with Collection
Determine Failing Nets
Identify Nets with High Deltas
DFM Rule Deck
Correlate Net Features to Net Yield
Identify Common Features
DesignDB
YieldDB
Generate Net Feature Statistics
Extract Net Yield Statistics
Update DFM Rule Deck
90
Advantages of Methodology

• Cost of Yield Learning
• No cost of designing test chip
• No cost of manufacturing a mask set
• No cost of running wafers
• No cost of special test chip testing
• Cycle Time
• No delay for test chip processing(uses
  production wafers)
• No re-spin of test chip for new features
• Accuracy
• The design features in the product accurately
  represent the features causing yield loss

91
CA Based Defect Density Estimation
92
Defect Distribution Estimation Flow
Defect Dist Eq Form
Iterate Equation Variables
Netlist
Extract Current Defect Dists
Calculate Predicted Net Yields
SCAN Test Data
Run SCAN Test with Collection
Determine Failing Nets
No
Correlate Predicted to Actual Yields
Extract Net Critical Areas
DesignDB
YieldDB
Calculate Critical Areas per Net
Extract Net Yield Statistics
Delta 0?
Update Defect Dists
Yes
93
Statistical Net Based Analysis
Source D. Appello, et al., ST Micro, Synopsys
94
Statistical Cell Based Analysis
FromD. Apello, et al., ST Micro
95
High Resolution Spatial Analysis
Stacked Die Level Fail Net Density Map
Stacked Shot Level Fail Net Density Map
Stacked Wafer Level Fail Net Density Map
96
State of the Art

• Statistical diagnostics of logic fails are a
  rapidly emerging design/defect learning
  technology
• Learning design-specific issues from product
  chips
• Statistical relevance with large number of
  samples
• Complement/enhance existing fab-oriented yield
  management systems
• Add intra-chip resolution and visibility
• Complement/enhance DFM and yield modeling
• Provide feedback and calibration
• Most existing solutions are home-grown at IDMs
• Challenging data security/access issue for
  fabless/foundry
• No integrated commercial solution yet

97
Vision of an Integrated Solution
Debug/FA Lab
Yield Management
Applications
Applications
APIs/Utilities
APIs/Utilities
Design Database
Fab Data Warehouse
WIP, Metrology, Test,
Design, design analysis,
Inspection, etc.
design intent, etc.
98
Vision of an Integrated Flow
ATPG Patterns
Fail Data
Suspect Nets,Fail Behavior
Single SuspectDisplay
DesignBrowsing/Navigation/Visualization
ATPG
detailed FaultLocalization volume
ATE
Failure Analysis
SampleSelection
Multi SuspectsDisplay
DefectIdentification
Yield Analysis Software Tool End Users Yield
Engineers Product Engineers Manufacturing
Engineers Design Engineers Test Engineers
Manufacturing Data Warehouse
WIP Data
Image Data
Metrology Data
Yield Analysis Software
99
Discussion
100
The End