Digital Filtering In Hardware

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Digital Filtering In Hardware

• Adnan Aziz

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Introduction

• Digital filtering vs Analog filtering
• More robust (process variations, temperature),
  flexible (bit precision, program), store
  recover
• Lower performance (esp high freq), more
  area/power, cannot sense, need data-converters
• Can perform digital filtering in hardware or
  software
• Software (DSP/generic microprocessors) flexible,
  less up-front cost
• Hardware (ASIC/FPGA) customized, cheaper in
  volume, lower area/power

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Applications

• Applications noise filtering, equalization,
  image processing, seismology, radar, ECC,
  audio/image compression
• Focus implementing difference equations
• No feedback FIR, feedback IIR
• Assume coefficient synthesis done
• Operate almost exclusively in time domain (FFT
  done)

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Evolution
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Various Representations

• 3-tap FIR
• Non terminating, repeatedly execute same code
• iteration Execute all operations, iteration
  period time to perform iteration, iteration
  rate inverse of iteration period
• sampling rate (aka throughput) number of samples
  per second, critical path max combinational
  delay (no wave pipelining!)
• Block Diagram
• Close to actual hardware interconnected
  functional blocks, potentially with delay
  elements between blocks

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Block Diagram
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Block Diagram
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Signal Flow Graph

• Unique source, sink (input and output)
• Edges represent const multiplier, delay
• Nodes represent I/O, adder, mult
• Useful for wordlength effects, less for
  architecture design

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SFG
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Dataflow Graph

• DFG
• Nodes computations (functions, subtasks)
• Edges datapaths
• Capture data-driven nature of DSP,
  intra-iteration and inter-iteration constraints
• Very general nonlinear, multirate, asynchronous,
  synchronous
• Difference from block diagram
• Hardware not allocated, scheduled in DFG

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DFG
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DFG
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Multirate DFG
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Iteration Bound

• In DFG, execution each node once in an iteration
• All nodes executed iteration
• Critical path combinational path with maximum
  total execution time (Note were reserving the
  term delay for sequential delay)
• Loop (cycle) path beginning and ending at same
  node
• Loop bound for loop L TL/WL
• Iteration Bound maximum of all loop bounds
• Lower bound on execution time for DFG (assuming
  only pipelining, retiming, unfolding)

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Iteration Bound
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Iteration Bound
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Iteration Bound
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2.3
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2.4
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2.5
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2.6
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2.7
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Pipeline and Parallelize

• Pipelining insert delay elements to reduce
  critical path length
• Faster (more throughput), lower power
• Added latency, latches/clocking
• Parallelism compute multiple outputs in a single
  clock cycle
• Faster, lower power
• Added hardware, sequencing logic

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Pipelining

• General applicable to microprocessor
  architectures, logic circuits, DFGs
• Have to place delays (flops) carefully
• On feed forward cutsets

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Pipelining
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Pipelining Parallel
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Pipelining
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Feed-forward Cutset
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Transposition
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Transposition
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Data Broadcast
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Fine-grain Pipelining
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Parallel Processing

• Process blocks at a time
• Clock period L Sample Rate

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Parallelism
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Parallelism
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Components
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Need for Parallelism
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Parallelism

• Why not use pipelining?
• May have a single large delay element that cannot
  be divided (communication between chips)
• Can use in conjunction with pipelining
• Relatively less efficient than pipelining (area
  cost and power savings)
• Note that weve skirted the issue of parallizing
  general DFGs
• Loops make life hard

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Parallelize Pipeline
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Area Efficiency
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Pipelining Processors

• Classic DLX processor
• ISA Load/Store or Mem Access
• 5 stages IF, ID, EX, MEM, WB
• Pipelining processors is hard
• Data hazards
• ADD r1, r2, r3 SUB r4, r5, r1
• Solution Use bypass logic
• LD r1, r2 ADD r4, r1, r2
• Solution?
• Branch hazards
• PC not changed till end of ID
• Solution redo IF (only) if branch taken
• Pipelining DFGs is easy (no control flow!)

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Pipelining Processors
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Retiming

• Basic idea (for logic circuits)
• Move flops back and forth across gates
• Use for clock period reduction, flop
  minimization, power minimization, resynthesis
• Same idea holds for DFGs
• Examples
• Algorithm
• C-slow retiming

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Retiming
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Retiming
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Cutset Retiming
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Cutset Retiming
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C-Slow Retiming
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Min Delay Retiming

• Formalize use notion of retiming function on
  nodes
• Amount of delay pushed back of node (can be
  negative think of as retardation function)
• Want to know if cycle time TC is feasible
• set up constraints
• Long paths have to be broken
• No negative delays on edges
• Solve using a custom ILP
• Uses efficient graph algorithms

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Unfolding

• Analagous to loop unrolling for programs
• for (I1 Ilt 5 I) aI bIcI
• Many benefits, at the price of potential increase
  in code size
• Look at 2-unfolding of
• Y(n) x(n) a y(n-9)
• General algorithm for J-unfolding a DFG
• Uses J nodes for each original node, new delay
  values
• Nontrivial fact algorithm works

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Unfolding
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Unfolding
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Applications

• Meet iteration bound
• When a single node has large execution time
• When IB is nonintegral

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Applications IB
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Application fractional IB
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Applications Parallelize

• Recall in Chapter 3, we never gave a systematic
  way of generating parallel circuits
• Loop unfolding gives a way

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Applications Bit-Digit

• Convert a bit-serial architecture to a
  digit-serial architecture

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Folding

• Trade area for time
• Use same hardware unit for multiple nodes in the
  DFG
• Example y(n) a(n) b(n) c(n)
• Need general systematic approach to folding
• Math formulation folding orders, folding sets,
  folding factors

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Folding
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Folding
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Folding
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Folding
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Folding
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Folding
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Register Minimization

• Consider DSP program that produces 3 variables
• a 1,2,3,4
• b 2,3,4,5,6,7
• c 5,6,7
• Number of live variables 1,2,2,2,2,2,2
• Intuitively, should be able to get by with 2
  registers
• However, DSP programs are periodic
• May have variable live across iterations

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Linear Lifetime Chart
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Lifetime Analysis Matrix
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Lifetime Chart Matrix
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Register Allocation Table
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Reg Assignment Matrix
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Reg Assignment Biquad
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Reg Assignment Biquad
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Pipelined Parallel IIR

• Feedback loops makes pipelining and parallelism
  very hard
• Impossible to beat iteration bound without
  rewriting the difference equation
• Example
• Pipeline interleaving of y(n1) a y(n) b u(n)
• Note that IB goes up, but can run multiple
  streams in parallel

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Pipeline Interleaved IIR
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Pipeline Interleaved IIR
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Pipeline Interleaved IIR
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Pipelining 1-st Order IIR

• Y(n) a y(n) u(n)
• Sample rate set by multiply and add time
• Can do better by look ahead pipelining
• Basically, changing the difference equation to
  get more delays in the loop
• Key functionality unchanged
• Best understood in terms of Z-transforms

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Pipelining 1-st Order IIR
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Pipelining 1-st Order IIR
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Pipelining High Order IIR

• Three basic approaches
• Clustered look-ahead
• Scattered look-ahead
• Direct synthesis with constraints

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Pipelining High Order IIR
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Pipelining High Order IIR
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Pipelining High Order IIR
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Pipelining High Order IIR
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Pipelining High Order IIR
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Pipelining High Order IIR
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Pipelining High Order IIR
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