Title: HIGH PERFORMANCE CMOS REALIZATION OF THE THIRD GENERATION CURRENT CONVEYOR CCIII
1HIGH PERFORMANCE CMOS REALIZATION OF THE THIRD
GENERATION CURRENT CONVEYOR (CCIII)
- S. Minaei1, M. Yildiz1,
- H. Kuntman2, S. Türköz2
- Dogus University, Department of Electronics and
Communication Engineering, - 81010, Acibadem, Kadiköy, Istanbul, TURKEY.
2. Istanbul Technical University, Faculty of
Electrical and Electronics Engineering,
Department of Electronics and Communication
Engineering, 80626, Maslak, Istanbul .
2ABSTRACT
- In this paper a new CMOS high performance
dual-output realization of the third generation
current conveyor (CCIII) is presented. The
proposed CCIII provides good linearity, high
output impedance at port Z and excellent
input/output current gain. PSPICE simulation
results using MIETEC 1.2? CMOS process model are
included to verify the expected values.
31. INTRODUCTION
- Current conveyors and unity-gain amplifiers are
widely used by analog designers - Signal processing
- Active network synthesis
- Recently third generation of this block has also
been proposed by Fabre et al 3.
- The third generation current conveyors (CCIIIs)
can be considered as a current controlled current
source with a unity gain.
4- High performance current mirrors are required in
the structure of the CCIII to provide - Good dynamic swing
- High output resistance which enables
cascadability.
- The main features of the CCIII are
- Low gain errors (high accuracy)
- High linearity
- Wide frequency response.
5- In this paper, we propose a novel implementation
of dual-output CCIII based on an improved
active-feedback cascode current mirrors (IAFCCM).
- The proposed CCIII is compared with the
conventional CCIII proposed in 3 and cascode
CCIII. It provides - High output resistance at port Z and
- High dynamic swing.
62. CIRCUIT DESCRIPTION
- The port relations of an ideal dual-output CCIII
is shown in Figure 1.
Figure 1. Electrical symbol of the CCIII
- The positive and negative signs define a positive
and negative current-controlled conveyor.
7- The conventional third generation current
conveyor is shown in Figure 2a 3.
- The conventional third generation current
conveyor is shown in Figure 2 3.
Figure 2a. Conventional third generation current
conveyor (CCIII).
Figure 2b. Conventional (CCIII) core view from X
and Y ports.
8- A major advantage of this CCIII is its simple
structure. - An important drawback of the conventional CCIII
is the finite output resistance (Roz). - The Z output resistance of this current conveyor
is, - Roz (rds21)//(rds22)
- where rdsi denotes the output resistance of
the ith transistor respectively. -
- Third generation current conveyor using cascode
current mirrors is shown in figure 3. - The cascode current mirrors between ports X-Y,
X-Z, and Y-Z- as shown in Figure 3. - Increase the accuracy of the current
transformations in the CCIII.
9Figure 3. Third generation current conveyor using
cascode current mirrors.
- The Z output resistance of the cascode CCIII is
calculated as - Roz ? (rds29 rds25 gm29)// (rds30rds26 gm30)
10- To increase the output resistance we propose a
new CCIII based on using improved active-feedback
cascode current mirror (IAFCCM) 10 in the
output stages of the conveyor. - The proposed CCIII is shown in Figure 4.
- The output resistance of the proposed CCIII is
calculated as - Roz gm32 gm30 rds31 rds32 (rds30// rds28)
//gm40 gm38 rds39 rds40 (rds38// rds34)
11Figure 4. The proposed third generation current
conveyor CCIII.
123. SIMULATION RESULTS AND COMPARISON
- The performance of the proposed CCIII shown in
Figure 4, is verified by SPICE simulation program
using, - MIETEC 1.2?m CMOS process model parameters
- PMOS transistor dimensions are W/L720µm/2.4µm
and, - NMOS transistor dimensions are W/L240µm/2.4µm.
- The voltage supply used for the proposed CCIII is
?2.5V.
- The main performances of the conventional,
cascode and proposed - CCIII are summarized in Table 1.
- From Table 1 it can be seen that the performance
of the proposed CCIII - is improved in terms of,
- Linearity
- gain accuracy
- output resistance.
13Figure 5. The relation between VX-VY for the
proposed CCIII
Figure 6. The relation between IX-IY-IZ for the
proposed CCIII.
Figure 7.The frequency response of the VX/VY
Figure 8. The frequency response of the IZ/IX
and IZ-/IX
14Table 1. Circuit performances.
154. CONCLUSION
- The proposed circuit uses improved
active-feedback cascode current mirrors (IAFCCM),
which increases output resistance at port-Z. - The proposed circuit is compared with the
conventional and cascode CCIIIs. The simulation
results confirm high performance of the circuits
in terms of - Linearity
- Voltage gain accuracy
- Current gain accuracy..
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