Evaluation of Redundancy Analysis Algorithms for Repairable Embedded Memories by Simulation

1
Evaluation of Redundancy Analysis Algorithms for
Repairable Embedded Memories by Simulation
Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, and
Cheng-Wen Wu

• Laboratory for Reliable Computing (LaRC)
• Electrical Engineering Department
• National Tsing Hua University

2
Outline

• Introduction
• RA Algorithm Evaluation by Simulation
• Simulation Time Reduction
• RA Design Verification
• Experimental Results
• Conclusions

3
Introduction

• Memory cores dominate the SOC silicon area
• Density of memory circuit and layout is much
  higher than logic
• Yield of memory cores thus dominates yield of the
  SOC
• Improving the yield of the memory cores is an
  increasingly important issue
• Effective built-in redundancy-analysis and
  self-repair methodologies need to be developed

4
Chip Area Breakdown

• Source International Technology Roadmap for
  Semiconductors (ITRS), 2000

5
Memory BISR Design

• What and how to design memory BISR?
• Memory spec
• Yield analysis
• Redundancy analysis algorithm develop
• Repair rate evaluation
• Spare elements selection
• BISR design
• Verification

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Redundancy Analysis

• RA algorithm is the main factor affecting repair
  efficiency

Faulty Memory
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RA Simulation and Verification
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Memory Specification File

• Memory Configuration
• Oriented 1 word-oriented or bit-oriented
• Word_Length 16
• Block_Size 256x16
• Block_Count 4
• Redundancy Design
• Spare_Rows 2
• Spare_Columns 8
• Defects and Faults Prob.
• Random_Defects 20
• Faulty_Rows 15
• Faulty_Columns 10
• Cluster_Faults 5
• Test Algorithms
• March

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Defect Injection

• Only point defects are assumed (no bulk defects)
• Defect count distributions
• Poisson, Gamma, Negative binomial, etc.
• Defect locations
• Randomly distributed on wafer/die
• Defect distribution is process dependent

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Fault Translation

• Defects lead to
• Faulty address decoder
• Faulty sense amplifier
• Faulty cells due to, e.g., coupling between
  bit-lines/word-lines
• Defects are translated to
• Single cell fault
• Faulty row
• Faulty column
• Cluster fault
• Etc.
• User can set the probability of each fault type

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Test Algorithm Simulation

• Fault information collected on-line
• Each Read operation provides different
  information
• Each fault can be detected by different Read
  operation
• BISR is an on-the-fly repair scheme
• The fault detection of test algorithm should be
  considered at RA simulation

12
Example March C Test
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Redundancy Analysis

• Our RA simulator evaluates different RA
  algorithms and report the respective repair rates
  and area overheads
• The RA algorithms are provided by the user
• Using function calls
• Spare element types
• Row, column, word, bit, etc
• Global/local
• Shared/non-shared

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Repair Rate Evaluation

• 3-D plot for repair rate

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Yield and Repair Rate

• Notations
• Y total yield A main memory area
• Ar redundant memory area
• Ac logic circuit of BISR area
• dm defect density of memory cores
• dc defect density of logic cores
• RR repair rate
• Yield can be derived from repair rate

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Graphical User Interface
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Simulation Time Reduction

• Criterion 1 N? Nsr Nsc? cant repair
• Criterion 2 Nsr Nsc Nfr Nfc Nsfc
  ?repairable

N? orthogonal cell count Nsr spare row
count Nsc spare column count Nfr faulty row
count Nfc faulty column count Nsfc single
faulty cell count
A faulty memory with N? 8
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RA Design Verification

• During BISR design, the verification is harder
• BISR includes BISD, BIRA, and Address
  Reconfiguration circuit
• Verification of each part can be done, but the
  whole BISR verification can not be done easily
• The pattern for BISR verification is diversified
  fault bit maps
• The simulator also can generate many
  diversification fault bit maps

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Verification Flow
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Bit-Oriented Memory Example

• Size 2048x55
• Single block
• Defects 1-20 (Poisson distribution)
• Faulty rows 15
• Single faulty cells 85
• Spare rows 1-10
• Spare columns 1-10

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Experimental Result
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Word-Oriented BISR

• Memory size 8K x 64 (8K x 32 x 2)
• Spare element (generate by memory compiler)
• 4 spare row
• 2 spare column group (4 column/group)
• RA algorithm split column in to 4 segments
• BISR gate count 5.6K
• Hardware overhead of spare element 4.57
• Hardware overhead of BISR 4.6
• Source A built-in self-repair scheme for
  semiconductor memories with 2-D redundancy, ITC
  2003.

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RR with Different Group Size
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Test Chip
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Conclusions

• We developed a simulator for evaluating the
  embedded-memory repair rates under different
• Redundancy analysis algorithms
• Spare-element configurations
• It helps evaluate built-in redundancy-analysis
  algorithms and develop self-repair schemes
• It also helps BISR design verification
• It is fast and effective