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Technology Insertion: Reliability and Qualification Considerations with Scaled CMOS New Electronic T

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Title: Technology Insertion: Reliability and Qualification Considerations with Scaled CMOS New Electronic T


1
Technology Insertion Reliability and
Qualification Considerations with Scaled CMOS
New Electronic Technologies and Insertion into
Flight Programs Workshop GSFC Jan. 30, 2007
  • Mark White
  • Strategic Initiatives Manager
  • Electronic Parts Engineering
  • Jet Propulsion Laboratory
  • California Institute of Technology

2
Overview
  • Technology Areas of Strategic Importance
  • Evolving Technological Needs
  • Technology Challenges
  • CMOS Scaling Trends Reliability Concerns
  • Scaled CMOS at Extreme Temperatures
  • Derating
  • FR Based Simulation
  • Intrinsic FM Drivers Effects
  • Managing Risk
  • Qualification Approaches
  • Technology Insertion Approach Framework
  • Technology Roadmap
  • Conclusions

3
Looking aheadMissions under development
ST-8 2008
Phoenix 2007
Dawn 2007
Kepler 2008
Ocean Surface Topography Mission 2008
Orbiting Carbon Observatory 2008
MSL 2009
WISE 2009
PlanetQuest Space Interferometer Mission, 2015
Juno 2010
Aquarius 2009
4
Technology Areas of Strategic Importance
  • Large Aperture Systems(Optical, IR and Radar
    Filled and Sparse)
  • Precision Flying
  • Detectors and Sensors
  • Cryogenic Systems
  • In-situ Planetary Exploration Systems
  • Planetary Protection Systems
  • Survivable Systems for ExtremeEnvironments
  • Deep Space Communications
  • Deep Space Navigation
  • Engineering Systems
  • Mission System Computing and Avionics
  • Utilization of High Capability Computing

5
Proposed New FrontiersMedium Missions

Flight projects need new technology
insertion guidance/guidelines to effectively
manage Risk
6
Evolving Technological Needs
  • High-bandwidth communication rates
  • Cost/risk modeling and validation
  • Integrated physics based models
  • Reliable long-life missions
  • Remote instruments
  • Systems for extreme environments
  • Electronics for high-radiation environments
  • Advanced mission computing hardware
  • New Part or Packaging Technology
  • An emerging technology where the required
    performance, reliability, and/or radiation
    characteristics have not yet been demonstrated or
    validated for a given application, environment,
    or mission.
  • Modern reliability approaches
  • Improved Modeling techniques
  • Enhanced Reliability tools and Simulation
    capability
  • Physics-of-Failure understanding of technology
    failure mechanisms
  • Novel screening qualification strategies
  • Application Risk Based - Criticality and
    Project Risk Posture
  • Optimized methodologies

7
Technology Insertion Challenges
  • Reliability concerns ultimately limit the
    scalability of any generation of microelectronics
    technology.
  • The design, fabrication and implementation/
    insertion of highly aggressive advanced
    microelectronics requires expert controls, modern
    reliability approaches and novel qualification
    strategies.
  • Modeling, simulation, device physics
    understanding of FMs, data gathering and
    analysis, and reliability prediction will provide
    the foundation for technology insertion of the
    next generation of scaled microelectronics.
  • NEPP cannot do it alone
  • Increased industry, academic, and governmental
    agency collaboration and partnering efforts are
    necessary

FIB Cross-section of a Xilinx Spartan FPGA
8
CMOS Scaling Trends Reliability Concerns
  • Reduced gate oxide thicknesses
  • Increased thermal/power densities
  • Reduced interconnect dimensions
  • Higher device operating temperatures
  • Increased sensitivity to defects and statistical
    process variations
  • Introduction of new materials with each new
    generation, replacing proven materials
  • e.g. Cu and low K inter-level dielectrics for Al
    and SiO2
  • Dramatic increase in processing steps with each
    new generation
  • approx. 50 more steps per generation and a new
    metal level every 2 generations
  • Rush to market - Less time to characterize new
    materials than in the past
  • e.g. reliability issues with new materials not
    fully understood and potential new failure modes
  • Manufacturers trends to provide just enough
    lifetime, reliability, and environmental specs
    for commercial industrial applications
  • e.g. 3-5 yr product lifetimes, trading off
    excess reliability margins for performance
  • Significant rise in the amount of proprietary
    technology and data developed by manufacturers,
    reluctance to share information with hi-rel
    customers
  • e.g. process recipes, process controls, process
    flows, design margins, MTTF
  • Increasingly difficult testability challenges due
    to device complexity

9
Increased Power Densities and Pronounced
Temperature Distributions
Power density distribution at gate-to-source and
drain-to-source biases of 0.0 and 3.0 V,
respectively. In this distribution, x 0
represents the start of the source region, x 6
10-7 m represents the end of the drain region,
and y 8 10-8 m represents the top surface of
the device.
Temperature distribution at gate-to-source and
drain-to-source biases of 0.0 and 3.0 V,
respectively, in the same region.
Increased power densities and higher junction
temperatures affect L/T reliability.
Electro-thermal Monte Carlo Simulation of
Submicron Si/SiGe Modulation-doped field effect
transistor (MODFETs). IEEE Transactions on
Electron Devices, Feb. 2007.
10
Scaled CMOS Performance at Extreme Temperatures
0.13um, 0.15um, 0.18um Xstr test structures
0.3um, 0.35um, 0.4um Xstr structures
  • Device performance changes at cryogenic
    temperatures
  • Higher drive current at low temperature higher
    saturation current Idsat (shown above)
  • Smaller channel length may have even larger Idsat
    increase
  • Lower leakage current at low temperature lower
    leakage from gate (not shown)

CMOS performance is better at low temperatures.
Reliability may be a concern.
PI Y. Chen - Technical Infrastructure Task
11
Scaled CMOS Reliabilityat Extreme Temperatures
  • Device reliability at cryogenic temperatures
  • Mechanism impact ionization induced hot hole
    hot electron pairs near drain area causing
    parametric degradation
  • Indicator substrate current, which increases
    with decrease of temperature

Reliability becomes a major concern. A factor of
67 decrease in device life may be expected from
RT to 20K.
PI Y. Chen - Technical Infrastructure Task
12
Device Physics Approach to Derating for
Reliability
  • Motivation
  • Understand the fundamental physics-of-failure
    mechanisms and the relative effect on L/T
    transistor, circuit, and product level
    reliability.
  • Develop meaningful derating criteria for
    deep-submicron scaled devices.
  • Determine the amount of margin to failure for
    assessing reliability.
  • Provide flight projects guidance for the reliable
    insertion of scaled devices.
  • How Derating Works
  • Derating reduces electrical, thermal and
    mechanical stresses relaxed stresses lead to
    improved reliability.
  • Why Derate?
  • Scaling has been explored to improve performance,
    not reliability voltage is not proportionally
    scaled and parts are operating hotter
  • Derating trades performance for reliability,
    appropriate derating is very important.
  • Commercial-Off-The-Shelf (COTS) devices are
    customized for the most popular markets High
    performance but short lifetime.
  • Aerospace avionics and military systems are
    second tier customers to main COTS suppliers, but
    we require reliable COTS.
  • We often need to operate COTS devices outside of
    specification limits, therefore we must
    understand the reliability trade-offs.

13
FR based Reliability Simulation Methodology
14
Intrinsic Failure MechanismDrivers Effects
  • Which failure mechanisms will dominate and what
    is the effect of FM interdependencies across
    applied stress conditions, environments and
    technologies?
  • HCD (Exp.)
  • Drivers Channel length width, oxide thickness,
    operating voltage, low temp.
  • Effect Increased substrate current (Isub),
    saturation drain current degradation (IDSAT),
    increase in Vth
  • EM (LN)
  • Drivers High temperature and current density in
    metal interconnects
  • Effect Metal migration leading to increased
    resistance, and open or short circuit
  • NBTI (Exp.)
  • Drivers Oxide thickness and high temperature
  • Effect Degraded (IDSAT) and transconductance
    (gm), increase in Ioff and Vth
  • TDDB (Weibull)
  • Drivers Oxide thickness, gate voltage, and high
    electric field, time
  • Effect Anode to cathode short through dielectric

Simulated Failure Distributions at Accelerated
Conditions
15
A Top Level Approach Managing Risk
Development of technologies, methodologies, and
guidelines for assessing, mitigating, and
managing risk
CALCE and the University of Maryland
16
Qualification Approaches
  • Traditional Mil-Std Part Qualification
  • A process to verify whether the anticipated
    performance and reliability will be achieved
    under expected conditions for some specified
    length of time.
  • Grp. A Electricals
  • Grp. C Die Related
  • 125C, 1,000 hr. life tests 
  • Grp. D Packaging Related
  • Grp. E Radiation Hardness
  • COTS Device Supplier WLR and Qualification
  • Goal Demonstrate some desired FIT rate
  • Screen out Infant Mortalities with high Vapp/Vnom
    ratio and elevated temperature to accelerate
    burn-in stress conditions
  • Wearout mechanisms are modeled (SPICE Sim.) for a
    given design, design is modified so that not any
    single wearout mechanism dominates (equally
    likely)
  • Qualification at the chip level
  • JP-001 (Foundry)

17
Qualification Approaches
  • Virtual Qualification
  • An integration of electrical, thermal, and
    mechanical performance degradation models and
    prior data to predict the L/T reliability in a
    specified operating environment.
  • Industrial Grade Qualification
  • Driven by automotive industry
  • AECQ-100
  • Application or Project Specific Qualification
  • Project determined risk levels (system level on
    down)
  • Criticality based
  • Risk mitigation with part, CCA, board level
    redundancy architectures, power and thermal
    management, design

18
Four Levels of Risk
  • System Level Availability
  • (dependent upon n components functioning on
    demand
  • Reliability function for non-repairable systems)
  • Circuit Functionality Level (electrical)
  • (dependent upon system demands, fault tolerance
    to parametric changes, design, and the ability of
    the parts
  • to operate within their specified parameters)
  • Part Level Reliability
  • (dependent upon time, robustness of design,
    stress levels,
  • and manuf., materials, process quality
    controls)
  • Transistor Level Reliability
  • (dependent upon time, stress levels,
  • and manufacturing, materials, process quality
    controls)

19
Technology Insertion Approach Framework
Collaborative Partnering efforts throughout the
hi-rel community (NASA, DOD, Suppliers, and
Academia)
  • Device Physics Approach to Understanding
    Technology
  • Reliability Analysis and Modeling
  • Simulation
  • Stress Testing
  • Data Gathering Analysis
  • Failure Analysis
  • Physics-of-Failure Mechanisms

Validation of Intrinsic Device Degradation
Mechanisms and Product Wearout Mechanisms for a
given Technology
20
Technology Insertion Approach Framework
  • What should a Technology Insertion Guide Address?
  • If SoC Processor, Programmable Logic, Memory
    functions
  • Design validation
  • S/W
  • Testing
  • Device architecture
  • Packaging risks
  • What supplier reliability and qualification
    protocols conditions has the technology been
    evaluated/exposed to?
  • Qualification status for the target market
  • Manufacturing/Production Line Maturity
  • ESD, Latch Up
  • Established materials processes or new?


21
Technology Insertion Approach Framework
  • What should a Technology Insertion Guide Address?
  • Radiation
  • - TID
  • - SEL, SEU
  • Established materials processes or new?
  • Intrinsic Device Degradation Mechanisms
  • - HC, NBTI, EM, TDDB, others
  • What target environment(s) is the technology well
    suited for?
  • Screening recommendations
  • Qualification recommendations
  • Derating
  • Project Guidance
  • Principle Goal Identify Risks of the Technology

22
Technology RoadmapProduct Technology Trends
DRAM, Microprocessor Flash Gate Length Trends
CMOS and Non-CMOS technologies will be integrated
into a single package (SiP)
ITRS 2005
23
Conclusions
  • Collaboration and partnering efforts are
    necessary to share the burden of technology
    assessment Leverage where possible
  • Gov. Agencies
  • Industry/suppliers
  • Academia
  • Aerospace/space industries must adapt to the
    commercial market offerings for SOTA technologies
  • Can no longer blindly follow heritage mil-spec
    methodologies
  • Higher reliance on risk mitigation strategies in
    the future, e.g., part, CCA, board level
    redundancy architectures, power and thermal
    management, design
  • Caution when assuming traditional acceleration
    models apply to new technologies Different
    failure mechanisms are exacerbated by different
    stress conditions, e.g. temp, voltage
  • Design for reliability, e.g. concept through
    application

24
Conclusions
  • Physics-of-failure based modeling,
    experimentation and validation needed to
    substantiate reliability prediction models,
    derating criteria and to support Technology
    Insertion Guides
  • Project Risk tolerance should be factored in to
    technology insertion decisions
  • Where is this work leading?
  • Project Risk Guidance
  • Improved microelectronic reliability prediction
    models and insertion guidelines to help flight
    projects make informed risk management decisions
  • Technology based optimized screening and
    qualification approaches
  • Sound derating principles and guidelines
  • Likely to evolve as technologies are scaled
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