ELVIS A Scalable, Loadable Custom Programmable Logic Device for Solving Boolean Satisfiability Probl

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ELVIS - A Scalable, Loadable Custom Programmable
Logic Device for Solving Boolean Satisfiability
Problems

• Mark Boyd and Tracy Larrabee

Jack Baskin School of Engineering
University of California Santa Cruz, CA
95064 mjboyd, larrabee_at_cse.ucsc.edu
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Satisfiability

• Satisfiability (SAT) is an important problem
• test pattern generation
• computer aided design
• logic minimization
• formal verification
• Given n bombers (with a limited range) and m
  targets to bomb, can we service all the targets?

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Satisfiability

• k-SAT formulas are of the form
• (ABC)(AB)(BC)(ABC)
• n3, of variables
• m4, of clauses
• k3, max of variables per clause
• For k 3, SAT is NP-Hard
• there is no known algorithm which determines the
  satisfiability of an arbitrary SAT problem in
  polynomial time

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Satisfiability

• The partial truth assignment A1, C1
• (TBT)(FB)(BF)(FBF)
• causes transitive implications
• B0 and B1, a contradiction

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Serial vs. Parallel Design

• Calculating transitive implications is critical
  for speedup
• GRASP (1996, Silva and Sakallah)
• Previous serial processor approach
• Calculates transitive implications serially
• Other excellent heuristics provide speedup
• Zhong (1998, Martonosi, Ashar, Malik)
• Calculates and broadcasts all direct transitive
  implications simultaneously in parallel

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Zhongs Design

• Shows significant speedup over GRASP by using
  massive, fine-grained parallelism
• Routes a unique implication circuit (IMP) for
  each SAT problem instance

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Zhongs Satisfiability

• (ABC)(AB)(BC)(ABC)

Bit Encoding B B Free 0
0 False 0 1 True 1 0 Contra 1 1
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ELVIS

• Easily Loaded Variable Implication Solver
• Two significant improvements over Zhongs
  original approach
• ONEACT reduces logic use by factor of k
• Bus Mask avoids NP-hard routing

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ELVIS ONEACT

• One Active Encoder, k-to-1 encoder
• Binary fan-in, ?(k) space complexity

• internal logic

• 16-to-1 ONEACT encoder

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Zhong Hole10

• For the clause (12345678910)
• Space complexity is (k-1)(k), ?(k )

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ELVIS Hole10

• ONEACT for (12345678910)
• Space complexity is k2k, ?(k)
• Key Result logic reduced by a factor of k

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ELVIS Design

• Clause Evaluation Circuit (CEC)

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ELVIS Design

• Variable Evaluation Circuit (VEC)

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ELVIS Components Wiring
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ELVIS Layout

• Programmable Logic Device
• 2-level AND-OR, like PLD
• bus mask for routing
• Majority CAM
• bus mask ternary CAM
• fanout to each cache entry

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Hardware Requirements


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n, of variables m, of clauses k, max of
variables per clause
where k is uniform, otherwise
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Latency Characteristics
n, of variables m, of clauses k, max of
variables per clause
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Future Work

• Implementation
• fast prototyping on Xilinx Virtex FPGAs
• heuristic version with priority variables
• SAT-server, accessible to other researchers
• Complete pipelining, ?(1) delay

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Competing Approach vs. ELVIS

• Design a place and route compiler which
• accepts k 3, n m/4
• always terminates in O(nm) time
• improves ELVIS space complexity
• loads new problems in O(m) time
• loads new clauses serially in constant time
• Is this impossible?

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Conclusion

• Purely polynomial design.
• Known timing and area characteristics.
• Loadable in ?(km) cycles, same as the size of the
  formula.
• IMP design compatible with any FSM.
• Reduces logic by factor of k vs. Zhong