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Test Generation for Digital Circuits

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Title: Test Generation for Digital Circuits


1
Test Generation for Digital Circuits
International Summer Academy 2008, Cottbus
Ondrej Novák TU Liberec and CTU in Prague, Czech
Republic contact novako3_at_fel.cvut.cz
2
Outline
  • Functional testing
  • Structure oriented testing
  • Deterministic test algorithms
  • Test compaction
  • Sequential circuits testing
  • Fault simulation

3
Domains and levels of a design
Circuit

Differential Equ
ations

Transistors

Masks

L


sourceSamiha Mourad Santa Clara University
4
Basic terminology
  • Digital signals that are useful to test potential
    faults in a circuit are test patterns.
  • A set of bits applied at a certain time is a
    test vector.
  • A test vector has to
  • - provoke a potential fault condition at a
    potential fault site
  • - propagate the fault to a primary circuit output
    to make it detectable.
  • The sum of all test vectors / test patterns to be
    applied to a specific device is called the test
    set.
  • Several (mostly two) test vectors need to be
    applied in a specific order to provoke and
    propagate certain fault effects. Then this pair
    (or triple) of vectors is called a test sequence.

5
Fault coverage
  • FC Number of faults covered by the test set
    divided by the total number of faults in a test
    set.
  • Problem The test set does not cover all
    possible faults (defects)

6
Required test properties
  • A test set should be as short as possible, but it
    should cover
  • relevant faults.
  • For production test many different faults
    should be found as
  • soon as possible, no fault diagnosis is
    necessary. Therefore
  • test patterns that cover multiple faults at a
    time are preferred.
  • For diagnostic test (e. g. prototype-test)
    patterns that may
  • excite specific fault conditions (single faults)
    are preferred.
  • Speed Length of the test set and the speed of
    test pattern
  • application response recording cost money
  • Cost For complex ICs, test-related costs may
    be from 30 to 50 of the overall production
    cost.

7
Testing methods
Structural approach
Functional approach
(Pseudo) exhaustive testing
(Weighted) random patterns
Path sensitiz-ation
SSBDD, Bool. satisfiability
Checking sequence
Boolean difference
not used
designs without DFT
ATPG
BIST
8
Functional approach
  • Exercising all possible input vector sequences,
    checking sequence
  • synchronizing sequence
  • homing sequence
  • distinguishing sequence
  • transition sequence
  • Pros zero hw overhead, patterns easy available,
    realistic test patterns (close to functional
    states, not overexcite the circuit)
  • Cons unacceptable high number of tests for
    complex circuits, final fault coverage is low

9
Concatenation of test tables
  • Circuit decomposition to basic testable units or
    composition of a system from testable modules
  • Creating test sets (tables) for the modules
  • Concatenation of basic test sets in such a way
    that every module inputs can be exited with
    supposed vectors and the output values are
    observable on system outputs

10
Concatenation of test sets
Z
Y
V
X
M1
M2
M3
V1 ........X1 V2 .......X2 Vn ......Xn
sensitive path1 sensitive path 2 sensitive path n
sensitive path 1 sensitive path 2 sensitive path n
X1 ........Y1 X2 .......Y2 Xm ......Ym
sensitive path 1 sensitive path 2 sensitive path m
Stimul 1 Stimul 2 Stimul m
Y1 ........Z1 Y2 .......Z2 Yk ......Zk
Stimul 1 Stimul 2 Stimul k
Stimul 1 Stimul 2 Stimul k
11
Testing with random patterns
  • high initial fault coverage efficiency

hard detectable faults
fault coverage
deterministic TPG
random TPG
number of patterns
figure E. Gramatova, Bratislava
12
Limits of random test
data H.-J.Wunderlich, Stuttgart
13
Random resistant faults
  • Random testability can be evaluated from the
    circuit scheme. The algorithm that estimates the
    testability cuts reconvergent fan outs and
    calculates probabilities of signal values
    (cutting algorithm).

SAF0
figure E. Gramatova, Bratislava
14
Testing a circuit with a random test
Deterministic TPG
Fault list
Fault simulation
Random TPG
Fault simulation is less complex computational
problem than test generation, it can help with
pattern selection.
15
Exhaustive and pseudoexhaustive test
  • exhaustively tests a circuit (exhaustive), all
    subcircuits (pseudoexhaustive)
  • (n,r) exhaustive test tests exhaustively every
    possible cone of combinational logic that has r
    or less inputs.
  • used in BIST

TEST PATTERN GENERATOR
1 2 3 . . .
n
r
r
r
1
2
u
CUT
16
Structure-oriented test algorithms
  • Exercises the minimal set of faults on each line
    of the circut
  • testing stuck-at-faults, delay faults, shorts ...
  • condition single faults
  • ATPG
  • generates test patterns
  • finds redundant or unnecessary logic
  • verifies circuit implementation
  • NP complete problem, the complexity is assumed
    to be exponential in the worst case.

17
Structural testing algorithm types
  • Symbolic Boolean Difference (reduced
    information about structure more functional)
  • Path sensitization
  • Boolean Satisfiability (not entirely) structural
    approach)
  • Structurally Synthesized Binary Decision
    Diagrams (SSBDD)

18
Boolean Difference
df(x)/dxi
  • df(x)/dx for xi 0 and df(x)/dxi pro xi1 are
    called residua
  • One of them is equal to the output value for the
    fault less circuit, the second one to output with
    a fault on xi
  • A fault is detected when the residua are
    complement
  • The test patterns can be derived from the
    following equations
  • xi df(x)/dxi 1 nebo xi ' df(x)/dxi 1

19
Path sensitization
path sensitisation
0
0 ? 1
1
force to 1
faulty output
good output
SAF0
Sensitive pathThe circuit output changes its
value in case of constant input values and a
fault on sensitive path appearance
figure E. Gramatova, Bratislava
20
Path sensitization
figureSamiha Mourad Santa Clara University
Observability and controllability measures
(SCOAP, ...) estimating the effort to set or
observe log. 1 or 0 are used in path
sensitization algorithms in order to find an
easiest sensitization path to PO and
justification to PIs.
21
D algorithm (Roth, 1964)
  • Formally describes conditions of the sensitive
    path existence
  • In D algorithm, the ATPG algebra has 5 symbols
    D, D, 0, 1, X
  • The sensitive path is created as a concatenation
    of so called D cubes
  • D cubes that describe the sensitive path through
    logic gates

22
D algorithm one pattern creation
  • A fault selection
  • Primitive D cube development
  • concatenation the D cube of the fault with a D
    cube of the log. element on the output of the
    faulty element
  • Reaching primary output by concatenated
    cubes(Sensitization)
  • Finding primary input values (Justification)
  • If not successfull - backtrack, new sensitization
    step

23
Podem (1981)
  • reduces the search space by expanding the
    decision tree only on primary inputs
  • introduction of so called D frontier,
  • measuring the simplicity of reaching a primary
    output heuristics for finding the easiest
    sensitive path

24
FAN (1983)
  • Decreases the number of backtracks
  • unique sensitization procedure
  • multiple backtracking procedure
  • immediate implications and justification
  • uses headlines (points, where a circuit can be
    partitioned)

25
Learning ATPG programs
  • Socrates (1988) static and dynamic learning. The
    learning procedure systematically sets circuit
    signals to different values and discovers what
    values are other signals implied.
  • Recursive learning (1995) learning procedure is
    called recursively

26
Search Space Abstractions in ATPGs
  • Binary decision tree
  • Binary decision diagram

figure Dirk Beyer , Vikipedia
27
Test generation with structurally synthesized BDDs
  • Testing all stuck-at faults corresponds to
    testing all the nodes in each SSBDD
  • Testing of a node consists of
  • Activating a path from the graph root to the node
  • Activating two paths from the tested node to
    terminal nodes corresponding to different
    logical values
  • Effective for structures that can be easily
    modelled by a graph. For multipliers less
    effective.

figure R. Ubar, Talinn
28
Boolean Satisfiability
  • Boolean satisfiability test generation approach
    is not structure oriented.
  • The fault free and faulty circuits are described
    by equations in conjunctive normal form together
    with the condition of the fault detection
  • A test vector can be found as a solution of
    concatenated conjunctive normal form composed by
    three original conjunctive forms.
  • A universal SAT solver can be used instead of an
    ATPG
  • The complexity of SAT solution depends on the
    number of literals in the OR clause of the form
    (2 SAT relation solvable in polynomial time)
  • SAT solver based test generators are competitive
    with the fastest structure oriented algorithms.
  • Commercial ATPG tool Tafertshofer, speed
    evaluation 25057 times faster than D alg.

29
Test compaction
  • Many combinational ATPGs use random patterns to
    achieve 60 fault coverage, then generate
    deterministic tests to obtain 100 coverage.
  • Some patterns are not sufficiently effective.
  • Fault simulation is performed in reverse order.
    Fault detecting patters are preserved.
    Significant test length reduction.
  • Additional static or dynamic heuristics based
    method is used for pattern compaction - replacing
    don't care values by 0 or 1. Further reduction by
    50 .

30
Sequential circuit test generation
  • Time frame expansion circuit can be tested by
    a combinational ATPG. Efficient for circuits
    described at the gate level, parallel computation
    often used for shortening the test generation
    time. Less efficient for cyclic structures,
    multiple-clocks and asynchronous circuits. 9
    value logic system required.
  • Simulation based methods test vectors randomly
    chosen and the fault coverage is simulated.
    Efficient for every circuit that can be
    simulated. Genetic algorithm can be used for
    vector selection.

m
m
m
k
I
Z
Copy 1
Copy 2
Copy j
n
n
n
SI
SO
n
SO
SI
Z
31
Fault simulation
  • Complexity of Fault Simulation
  • In general, proportional to the following factors
  • F number of faults
  • P number of test patterns
  • G number of gates
  • Complexity approximately O(G3)
  • More difficult than logic simulation by the
    factor F.
  • easier than test generation
  • The complexity can be greatly reduced by
  • fault dropping
  • advanced techniques.

32
Effectiveness of simulation techniques
table Chien-Mo James Li Graduate Institute of
Electronics Engineering National Taiwan University
33
Conclusion
  • Quality of test vectors and the CPU time of their
    generation depends on the circuit testability
    (SCOAP measures).
  • Path sensitization algorithms can be used for
    combinational circuits, for sequential circuits
    with multi clock domains, internal cycles and
    asynchronous behavior are less effective.
  • Algorithms based on solution of the SAT problem
    are the most effective for the biggest circuits.
  • Fault simulation together with a genetically
    driven searching of test vectors could be a
    solution for testing sequential circuits.
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