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The Instruction Set Architecture Level

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Hardware wants simple clean from point of view of components ... Legacy. Split memory data/instructions. Linear. Access modes. Registers ... – PowerPoint PPT presentation

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Title: The Instruction Set Architecture Level


1
The Instruction Set Architecture Level
  • Chapter 5

2
Tradeoffs
  • Hardware wants simple clean from point of view of
    components
  • Software wants complex, fast, extended
    instructions
  • Sales (customers) want backward compatibility

3
Good ISA
  • Implement efficiently in current and future
    technology
  • Good target for compiled code

4
Properities of ISA level
  • Memory model
  • Registers
  • Data Types
  • Instructions
  • Security
  • In Addition
  • Pipeline
  • Superscalar
  • Etc.
  • Some officially documented (SPARC)

5
ISA Level
  • The ISA level is the interface between the
    compilers and the hardware.

6
Memory Models
  • An 8-byte word in a little-endian memory. (a)
    Aligned. (b) Not
  • aligned. Some machines require that words in
    memory be aligned.

7
Memory Model
  • Alignment
  • Legacy
  • Cache logic
  • Synchronization
  • Serialized
  • other
  • Legacy
  • Split memory data/instructions
  • Linear
  • Access modes

8
Registers
  • ISA always visible to micro architecture
  • Micro level some visible to ISA
  • Register types
  • General
  • Specific
  • Mixed (EDX)
  • Flag Register PSW
  • N negative
  • Z Zero
  • V oVerflow
  • C Carry
  • A Auxilary cary
  • P Parity

9
ISA Modes
  • Pentium modes
  • Real mode 8088 compatibility
  • Virtual 8086 mode run multiple 8088 protected
  • Protected mode all features on
  • Memory 16K different 4 GB address spaces
  • Limited by OS

10
Overview of the Pentium 4 ISA Level
  • The Pentium 4s primary
  • registers.

11
UltraSparc III ISA
  • 64 bit machine
  • 264 linear memory larger than needed
  • Register windows emulate call stack in
    registers
  • Load/store architecture

12
Overview of the UltraSPARC III ISA Level (1)
  • The UltraSPARC IIIs general registers.

13
Overview of the UltraSPARC III ISA Level (2)
  • Operation of the
  • UltraSPARC III
  • register windows.

14
8051 Architecture
  • 64K for program
  • 64K for data
  • Split for ROM/RAM combination
  • 4 sets of registers ( 8 registers per set)
  • Allows for quick interrupt
  • No built in security
  • Bit Addressable memory
  • Registers and IO use memory space
  • Some registers general and some dedicated

15
Overview of the 8051 ISA Level
  • (a) On-chip memory organization for the 8051.
  • (b) Major 8051 registers.

16
Data Types on the Pentium 4
  • The Pentium 4 numeric data types.
  • Supported types are marked with .

17
Data Types on the UltraSPARC III
  • The UltraSPARC III numeric data types.
  • Supported types are marked with .

18
Data Types on the 8051
  • The 8051 numeric data types.
  • Supported types are marked with .

19
Instruction Formats (1)
  • Four common instruction formats
  • (a) Zero-address instruction. (b) One-address
    instruction
  • (c) Two-address instruction. (d) Three-address
    instruction.

20
Instruction Formats (2)
  • Some possible relationships between instruction
    and word length.

21
Instruction Design Criteria
  • Stack based vs. many registers
  • Now vs. the future
  • Short are better than long (within limits)
  • Leave room for expansion
  • Upper limit (cache band width)/instruction
    length
  • Bits in address field

22
Expanding Opcodes (1)
  • An instruction with a 4-bit opcode and three
    4-bit address fields.

23
Expanding Opcodes (2)
  • An expanding opcode allowing 15 three-address
    instructions, 14
  • two-address instructions, 31 one-address
    instructions, and 16 zero-address instructions.
    The fields marked xxxx, yyyy,
  • and zzzz are 4-bit address fields.

24
Pentium opcodes
  • Highly complex and irregular
  • 6 variable length fields, 5 are optional
  • Only one operand in memory

25
The Pentium 4 Instruction Formats
  • The Pentium 4 instruction formats.

26
UltraSPARC instruction format
  • All 32 bit
  • Aligned in memory
  • Up to 3 operands in instruction

27
The UltraSPARC III Instruction Formats
  • The original SPARC instruction formats.

28
8051 Instruction format
  • 6 formats
  • 1,2 or 3 bytes long
  • Original 8088 compare to Pentium structure

29
The 8051 Instruction Formats
  • The 8051 instruction formats.

30
Address modes
  • Immediate - embedded constant
  • Direct full address in instruction
  • Register Addressing refers to register instead
    of memory
  • Register Indirect addressing address in
    register
  • Indexed Addressing memory iindexed by register
  • Based-Index Addressing add 2 register plus an
    optional offset
  • Stack Addressing
  • Index mode branch - offset

31
Addressing
  • An immediate instruction for loading 4 into
    register 1.
  • Register Indirect Addressing a generic assembly
    program for
  • computing the sum of the elements of an array.

32
Indexed Addressing (1)
  • A generic assembly program for computing the OR
    of Ai AND Bi for two 1024-element arrays.

33
Indexed Addressing (2)
  • A possible representation of MOV R4,A(R2).

34
Reverse Polish Notation (1)
  • Each railroad car represents one
  • symbol in the formula to be
  • converted from infix to reverse
  • Polish notation.

35
Reverse Polish Notation (2)
  • Decision table used by the infix-to-reverse
    Polish notation algorithm

36
Reverse Polish Notation (3)
  • Some examples of infix expressions and
  • their reverse Polish notation equivalents.

37
Evaluation of Reverse Polish notation Formulas
  • Use of a stack to evaluate a reverse Polish
    notation formula.

38
Orthogonality of Opcodes and Addressing Modes (1)
  • A simple design for the instruction formats of a
    three-address machine.

39
Orthogonality of Opcodes and Addressing Modes (2)
  • A simple design for the instruction formats
  • of a two-address machine.

40
The Pentium 4 Addressing Modes (1)
  • The Pentium 4 32-bit addressing modes. Mx
  • is the memory word at x.

41
The Pentium 4 Addressing Modes (2)
  • Access to ai.

42
Discussion of Addressing Modes
  • A comparison of addressing modes.

43
Instruction types
  • Data movement instructions
  • Dyadic Operations add, sub, mul, div, and
  • Monadic Operations one operand and one result
    (shift)
  • Comparison and Conditional branch
  • Procedure calls
  • Loop Control
  • Input/Output

44
Loop Control
  • (a) Test-at-the-end loop.
  • (b) Test-at-the-beginning loop.

45
Input/Output (1)
  • Device registers for a simple terminal.

46
Input/Output (2)
  • An example of programmed I/O.

47
Input/Output (3)
  • A system with a DMA controller.

48
The Pentium 4 Instructions (1)
  • A selection of the Pentium 4 integer instructions.

49
The Pentium 4 Instructions (2)
  • A selection of the Pentium 4 integer instructions.

50
The Pentium 4 Instructions (3)
  • A selection of the Pentium 4 integer instructions.

51
The Pentium 4 Instructions (4)
  • A selection of the Pentium 4 integer instructions.

52
The UltraSPARC III Instructions (1)
  • The primary UltraSPARC III integer instructions.

53
The UltraSPARC III Instructions (2)
  • The primary UltraSPARC III integer instructions.

54
The UltraSPARC III Instructions (3)
  • The primary UltraSPARC III integer instructions.

55
The UltraSPARC III Instructions (4)
  • The primary UltraSPARC III integer instructions.

56
The UltraSPARC III Instructions (5)
  • The primary UltraSPARC III integer instructions.

57
The UltraSPARC III Instructions (6)
  • Some simulated UltraSPARC III instructions.

58
8051 Instructions (1)
  • The 8051 Instruction set.

59
8051 Instructions (2)
  • The 8051 Instruction set.

60
8051 Instructions (3)
  • The 8051 Instruction set.

61
8051 Instructions (4)
  • The 8051 Instruction set.

62
8051 Instructions (5)
  • The 8051 Instruction set.

63
Sequential Flow of Control and Branches
  • Program counter as a function of time (smoothed).
  • (a) Without branches. (b) With branches.

64
Recursive Procedures (1)
  • Initial configuration for the Towers of Hanoi
    problem for five disks.

65
Recursive Procedures (2)
  • The steps required to solve the Towers of Hanoi
    for three disks.

66
Recursive Procedures (3)
  • The steps required to solve the Towers of Hanoi
    for three disks.

67
Recursive Procedures (4)
  • A procedure for solving the Towers of Hanoi.

68
Recursive Procedures (5)
  • The stack at several points during the execution
    of Fig. 5-42.

69
Coroutines (1)
  • When a procedure is called,
  • execution of the procedure
  • always begins at the first
  • statement of the procedure.

70
Coroutines (2)
  • When a coroutine is resumed, execution begins at
    the
  • statement where it left off the previous time,
    not at the beginning.

71
Interrupts
  • Time sequence of multiple interrupt example.

72
Towers of Hanoi in Pentium 4 Assembly Language (1)
. . .
  • Towers of Hanoi for Pentium 4.

73
Towers of Hanoi in Pentium 4 Assembly Language (2)
. . .
. . .
  • Towers of Hanoi for Pentium 4.

74
Towers of Hanoi in Pentium 4 Assembly Language (3)
. . .
  • Towers of Hanoi for Pentium 4.

75
Towers of Hanoi in UltraSPARC III Assembly
Language (1)
. . .
  • Towers of Hanoi for UltraSPARC III.

76
Towers of Hanoi in UltraSPARC III Assembly
Language (2)
. . .
. . .
  • Towers of Hanoi for UltraSPARC III.

77
Towers of Hanoi in UltraSPARC III Assembly
Language (3)
. . .
  • Towers of Hanoi for UltraSPARC III.

78
Reducing Memory References
  • The Itanium 2s registers.

79
Instruction Scheduling
  • An IA-64 bundle contains three instructions.

80
Reducing Conditional Branches Predication (1)
  • (a) An if statement.
  • (b) Generic assembly code for a).
  • (c) A conditional instruction.

81
Reducing Conditional Branches Predication (2)
  • (a) An if statement.
  • (b) Generic assembly code for a).
  • (c) Conditional instruction.

82
Reducing Conditional Branches Predication (3)
  • (a) An if statement.
  • (b) Generic assembly code for a).
  • (c) Predicated instruction.
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