DATA MANIPULATION

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DATA MANIPULATION

• Tian-Li Yu
• tianliyu_at_cc.ee.ntu.edu.tw
• Department of Electrical Engineering
• National Taiwan University

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Motherboard
CPU Slot
Memory Slot
From http//www.asus.com.tw
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Computer architecture

• CPU (central processing unit)
• Registers
• Memory
• Bus
• Motherboard

Textbook, Figure 2.1
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Adding values stored in memory
Textbook, Figure 2.2
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Machine instructions

• Data transfer
• LOAD, STORE, I/O
• Arithmetic/logic
• AND, OR, ADD, SUB, etc.
• SHIFT, ROTATE
• Control
• JUMP, HALT
• RISC (PPC, SPARC) vs. CISC (x86, x86-64)

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Architecture of a simple machine
Textbook, Figure 2.4
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Example of a machine instruction
Textbook, Figure 2.5
Store (3) the content of register no. 5 to the
memory cell addressed A7
Memory reference 28256 cells (bytes)
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Adding two values revisited
Possible assembly
Possible C
LOAD 5, 6C LOAD 6, 6D ADD 0, 5, 6 STORE 0,
6E HALT
c a b
Textbook, Figure 2.7
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Program execution

• Instruction register, program counter
• Machine cycle

• Clock
• Benchmarking

Textbook, Figure 2.8
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Fetch
Textbook, Figure 2.7
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Logic/bit operations

• Masking

AND 01010101 00001111 00000101 Setting the
first 4 bits to 0.
OR 01010101 00001111 01011111 Setting the
latter 4 bits to 1.
XOR 01010101 00001111 01011010 Inverting the
latter 4 bits.
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Shift/Rotation

• Logic shift
• 10100000 ? 01010000 (right)
• ? 01000000 (left)
• Arithmetic shift
• 10100000 ? 11010000 (right)
• ? 11000000 (left)
• Rotation
• 10100000 ? 01010000 (right)
• ? 01000001 (left)

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Controller

• Specialized
• General USB, FireWire

Textbook, Figure 2.13
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Memory-mapped I/O

• I/O as LOAD, STORE

Textbook, Figure 2.14
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Communication with other devices

• DMA direct memory access
• Once authorized, controllers can access data
  directly from memory without notifying CPU.
• Hand shaking
• 2-way communication
• Coordinating activities
• Parallel/Serial
• Transfer rate bit per second (bps, Kbps, Mbps,
  etc)

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Pipelining

• Throughput increased
• Total amount of work accomplished in a given
  amount of time.
• Example pre-fetching
• Issue conditional jump

Time
Fetch
Decode
Execute
Fetch
Decode
Execute
Fetch
Decode
Execute
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Parallel/distributed computing

• Parallel
• Multiprocessor
• MIMD, SISD, SIMD
• Distributed
• Linking several computers via network
• Separate processors, separate memory
• Issues
• Data dependency
• Load balancing
• Synchronization
• Reliability

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To parallel xor not to parallel

• declare A0A99
• input A0, A1, A2
• for (i 3 i
• Ai Ai-2 Ai-3

declare A0A99 input A0 for (i 1 ii) Ai Ai-1 2
How to parallel?
for (i 3 iAi-3 Ai1 Ai-1 Ai-2 A99
A97 A96
CPU 0
2 CPUs
CPU 1
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Speedup Scaling

• Speedup
• (Amdahl's law)

Gain
Number of processors
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Exercises

• Ch 2 5, 7, 15, 23, 28, 33, 39, 44, 48