EET 3350 Digital Systems Design Textbook: John Wakerly Chapter 9: 9.29.4

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EET 3350 Digital Systems Design Textbook John
Wakerly Chapter 9 9.2-9.4

• Static read/write memories
• Dynamic read/write memories

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Agenda

• RAM
• SRAM
• DRAM
• Variations
• DIMM
• SIMM
• RIMM
• RDRAM
• NVRAM
• PSRAM

Read/Write Memory
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Random Access Memory (RAM)

• For most applications, main memory is a
  collection of RAM chips
• These are volatile, switch the machine off and
  the contents in this form of memory are lost
• There are three basic types of RAM
• Dynamic RAM (DRAM)
• Static RAM (SRAM)
• Non-volatile RAM (NVRAM RAM battery)

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Random Access Memory (RAM)

• Read/Write Memory
• Access time is independent of bits location
• Volatile lose their content when power is
  removed
• Static RAM (SRAM)
• Memory behaves like Latches or Flip-Flops
• Data remains stored as long as power applied
• Dynamic RAM (DRAM)
• Charged or discharged capacitor
• Memory lasts only for a few milliseconds
• Data must be refreshed periodically by reading
  and rewriting

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Static RAM (SRAM)

• Each bit (or the cell that stores the bit) is
  represented by a Flip-Flop (or, more accurately,
  a Latch)
• The cell's output is maintained until either
  altered to a new value or the power is turned off
• When compared to Dynamic RAM (DRAM)
• More complex
• More expensive

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Static RAM (SRAM)

• Since storage cells in SRAM are made of Latches
  they do not require refreshing in order to keep
  their data
• The problem is that each cell requires at least
  six transistors to build and the cell holds only
  one bit data
• The capacity of SRAM is far below DRAM
• SRAM is widely used for cache memory

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SRAM

• Basic structure and logic symbol for a 2n x b SRAM

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SRAM Operation

• Individual bits are D latches, not edge-triggered
  D flip-flops
• Fewer transistors per cell
• Implications for write operations
• Address must be stable before writing cell
• Data must be stable before ending a write

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SRAM Operation

• SEL and WR asserted
• IN data stored in D-latch (Write)
• SEL only asserted
• D-latch output enabled (Read)
• SEL not asserted
• No operation

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SRAM

• SRAM Static RAM
• Memory cell uses a Latch to store bit
• Requires six (6) transistors
• Holds data as long as power supplied

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SRAM

• WL word line, BL bit line

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SRAM

• Storage is modeled by an SR-Latch (configured as
  a D-Latch)
• Control logic
• One memory cell per bit

For Select 0, the stored content is held. For
Select 1, the stored content is determined by
values on B and B The outputs are gated by the
Select line also.
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SRAM

• Cells connected to form 1 bit position
• Word select gates one latch from address lines
• B (and B) set by R/W, Data in and Bit select
• When R/W 0 and Bit Select 1,
• then if Data in 1 ? the latch will be set
• (i.e., a 1 is written)

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SRAM

• Bit slice can become a module
• Basically bit slice is a one dimensional array of
  memory
• What type of hardware do we need to access one
  row at a time?

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SRAM

• 16 x 1 RAM
• 4 address lines required to access 16 locations
• A Decoder is added to select the different words
  (each 1 bit wide)
• For 16 words we need a 4-to-16 line Decoder

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SRAM

• 16 X 1 as 4 X 4 Array
• Practical memories contain thousands of words
• If RAM gets large, there is a huge decoder
• Also run into chip layout issues
• How can we change the structure of memory to
  solve this problem?
• Rearrange the memory into 2D i.e., matrix
  layout

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SRAM

• Change to 8 X 2 RAM
• Minor change in logic
• Example
• Try addressing 011 on board
• Cells 6,7 are chosen for reading or writing

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SRAM Array

• Internal structure of an 8 x 4 static RAM
• As with ROM, the decoder selects a particular row
• Outputs are tri-state buffered and controlled by
  an enable input

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SRAM Control Lines

• Chip select
• Output enable
• Write enable

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SRAM Read Timing

• Similar to ROM read timing
• tAA access time from address
• tACS access time from chip select
• tOE/tOZ output-enable/disable time
• tOH output-hold time

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SRAM Write Timing

• tAS/tAH address setup/hold time before/after
  write
• tCSW chip-select setup before end of write
• tWP write-pulse width
• tDS/tDH data setup/hold time before/after write

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SRAM Write Timing

• Address must be stable before and after
  write-enable is asserted
• Data is latched on trailing edge of (WE CS)

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Bidirectional Data In and Out Pins

• Use the same data pins for reads and writes
• Especially common on wide devices
• Makes sense when used with microprocessor buses
  (also bidirectional)

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SRAM Devices

• Similar to ROM packages

28-pin DIPs
32-pin DIPs
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Synchronous SRAMs

• Use latch-type SRAM cells internally
• Put registers in front of address and control
  (and maybe data) for easier interfacing with
  synchronous systems at high speeds
• e.g., Pentium cache RAMs

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SRAM Datasheet

• HM62256A is a CMOS static RAM organized 32-K
  8-bit
• High speed Fast Access time 85/100/120/150 ns
  (max)
• Low Power
• Standby 5 µW (typ) (L/L-SL version)
• Operation 40 mW (typ) (f 1 MHz)
• Single 5V supply

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SRAM Datasheet

• HM62256 package and block diagram

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Dynamic RAM (DRAM)

• Commonly used in main memory.
• A logical '1' is used to charge a capacitor, and
  this holds the device in its switched on (or
  positive state).
• The capacitor will lose it's charge with time so
  the capacitor has to constantly refreshed to keep
  the switched on state.
• If a logical '0' is to be stored the capacitor is
  discharged.

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Dynamic RAM (DRAM)

• The use of a capacitor as a means to store data
• Cuts down the number of transistors needed to
  build cell
• However, it requires constant refreshing due to
  leakage
• Advantage
• High density (capacity)
• Cheaper cost per bit
• Lower power consumption per bit
• Disadvantage
• Must be refreshed periodically
• While it is being refreshed, the data can not be
  accessed

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DRAM

• DRAM Dynamic RAM
• Uses MOS transistor and capacitor to store bit
• More compact than SRAM
• Refresh required due to capacitor leak
• Typical refresh rate 15.625 microsecond
• Slower to access than SRAM

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Dynamic Memory Cell

• An SRAM cell has a bi-stable latch that requires
  from four to six transistors to be built.
• To deliver the higher memory density required for
  computer systems, a single transistor memory cell
  was developed for the DRAM.

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Writing 1 in a Dynamic Memories

• To store a 1 in this cell, a HIGH voltage is
  placed on the bit line, causing the capacitor to
  charge through the on transistor.

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Writing 0 in a Dynamic Memories

• To store a 0 in this cell, a LOW voltage is
  placed on the bit line, causing the capacitor to
  discharge through the on transistor.

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Destructive Reads

• To read the DRAM cell, the bit line is precharged
  to a voltage halfway between HIGH and LOW, and
  then the word line is set HIGH.
• Depending on the charge in the capacitor, the
  precharged bit line is pulled slightly higher or
  lower.
• A sense amplifier detects this small change and
  recovers a 1 or a 0.

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Recovering from Destructive Reads

• The read operation discharges the capacitor.
• Therefore a read operation in a dynamic memory
  must be immediately followed by a write operation
  of the same value read to restore the capacitor
  charges.

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Forgetful Memories

• The problem with this cell is that it is not
  bi-stable
• only the state 0 can be kept indefinitely, when
  the cell is in state 1, the charge stored in the
  capacitor slowly dissipates and the data is lost.

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DRAM Charge Leakage

• Typical devices require each cell to be refreshed
  once every 4 to 64 mS
• During suspended operation, notebook computers
  use power mainly for DRAM refresh

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DRAM Packaging

• Packaging in DRAM
• To reduce the number of pins needed for address,
  multiplex / demultiplexing is used
• Method is to split the address into half and send
  in each half of the address through the same pins
  ? requires fewer pins
• Internally, DRAM is divided into a square of rows
  and columns, the first half of the address is
  called the row and the second half is called the
  column
• Organization of DRAM
• Most DRAM are x 1 and x 4

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DRAM

• DRAM read timing

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DRAM

• DRAM refresh timing

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DRAM

• DRAM write timing

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DRAM-Chip Internal Organization
64K x 1 DRAM
multiplex 16-bit addressas 8-bit row
selectorand 8-bit column selector
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RAS/CAS Operation

• Row Address Strobe, Column Address Strobe
• n address bits are provided in two steps using
  n/2 pins, referenced to the falling edges of
  RAS_L and CAS_L
• Traditional method of DRAM operation for 20 years
• Now being supplanted by synchronous, clocked
  interfaces in SDRAM (synchronous DRAM)

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SDRAM Timing (Read)

• PRE precharge (bit line)
• ACTV row-address strobe and activate bank
• READ column address and read command

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SDRAM Timing (Write)

• PRE precharge (bit line)
• ACTV row-address strobe and activate bank
• WRITE column address and write command

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Types of RAM

• RAM chips on a PC motherboard

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Types of RAM

• A better approach is to use removable modules

RAM
RAM
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Types of RAM

• RAM modules come in many forms
• An alphabet soup of variations

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Types of RAM

• EDO DRAMs
• EDO DRAM Extended Data Out DRAM
• The most common type of asynchronous DRAM
• EDO memory has had its timing circuits modified
  so one access to the memory can begin before the
  last one has finished
• EDO DRAM has been replaced by SDRAM

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Types of RAM

• FPM DRAMs
• FPM DRAM Fast Page Mode DRAM
• A row of the DRAM can be kept "open" by holding
  /RAS low while performing multiple reads or
  writes with separate pulses of /CAS.
• Successive reads or writes within the row do not
  suffer the delay of precharge and accessing the
  row.

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Types of RAM

• Synchronous DRAM (SDRAM)
• SDRAM has a synchronous interface
• SDRAM replaced DRAM, FPM, and EDO
• SDRAM is an improvement because it synchronizes
  data transfer between the CPU and memory.
• It waits for a clock pulse before transferring
  data and is therefore synchronous with the
  computer system bus and processor.
• This greatly improves performance over
  asynchronous DRAM.

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Types of RAM

• SDRAM
• SDRAM/ESDRAM synchronous and enhanced
  synchronous DRAM
• SDRAM modules usually come in the form of 168-pin
  DIMMs

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Types of RAM

• Double Data Rate SDRAM (DDR SDRAM)
• DDR SDRAM is a newer form of SDRAM that can
  theoretically improve memory clock speed to 200
  megahertz (MHz) or more.
• Sends and receives data twice as often as common
  SDRAM.
• This is achieved by transferring data on both the
  rising edge and the falling edge of a clock
  cycle.
• DDR memory is being phased out and replaced by
  DDR2 memory.
• DDR memory modules usually take the form of
  184-pin DIMMs.

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Types of RAM

• DDR2 SDRAM
• Second generation DDR memory provides greater
  bandwidth and other new features such as On-Chip
  Termination (OCT).
• 4 bits of data are moved from the memory array to
  the I/O buffers (per data line) each core cycle.
• This can be described as 4-bit prefetch, as
  opposed to the single-bit fetch in SDRAM and
  2-bit prefetch with DDR SDRAM.
• DDR2 memory modules are 240-pin DIMMs.

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Types of RAM

• DDR3 SDRAM
• Third generation DDR memory
• DDR3 provides higher bandwidth than DDR2 due to
  the 8-bit prefetch buffer (4-bit prefetch of
  DDR2, and 2-bit of DDR).
• Uses lower operating currents and voltages (1.5V,
  compared to 1.8V of DDR2) and thus enhances
  thermal performance.
• DDR3 memory modules take the form of 240-pin
  DIMMs, and are not compatible with DDR2 memory
  slots.

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Types of RAM

• Single Inline Memory Module (SIMM)
• SIMM is a memory module with 72 or 30 pins. SIMMs
  are considered legacy components

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Types of RAM

• Dual Inline Memory Module (DIMM)
• DIMM is a memory module with 168 pins.
• DIMMs are commonly used today and support 64-bit
  transfer.

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Types of RAM

• Rambus Inline Memory Module (RIMM)
• RIMM is a 184-pin memory module that uses only
  the RDRAM
• This is a type of synchronous DRAM created by the
  Rambus Corporation.
• RDRAM features an architecture designed to
  achieve high bandwidth, it is used in the Sony
  PlayStation 2, early Pentium 4 desktop systems
  and other applications.
• The XDR DRAM, RDRAM's successor, is used in IBM's
  Cell processor and Sony PlayStation 3.

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Types of RAM

• RDRAM is also mainly used for capacity expansion
  of old desktop systems and often come in the form
  of 184-pin RIMMs/Rambus Inline Memory Modules
  (16bit).

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Types of RAM

• PSRAM Pseudo-Static RAM
• DRAM with built-in memory refresh and
  address-control circuitry to make it behave
  similarly to static RAM
• Popular low-cost high-density alternative to SRAM
• Combines the high density of DRAM with the ease
  of use of true SRAM.
• PSRAM (made by Numonyx) is used in the Apple
  iPhone and other embedded systems

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Types of RAM

• NVRAM Nonvolatile RAM
• Holds data after external power removed
• Battery-backed RAM
• SRAM with own permanently connected battery
• writes as fast as reads
• no limit on number of writes unlike nonvolatile
  ROM-based memory
• SRAM with EEPROM or flash
• stores complete RAM contents on EEPROM or flash
  before power turned off

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Assignments

• Read section 9.5