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A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Networks

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Title: A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Networks


1
A Case for Using Signal Transition Graphs for
Analysing and Refining Genetic Networks
  • Richard Banks, Victor Khomenko and Jason Steggles
  • School of Computing Science,
  • Newcastle University, UK

2
Overview
  • Modelling genetic regulatory networks using
    Boolean networks (BNs).
  • Problems with BN approach.
  • Asynchronous circuit design techniques.
  • A refinement approach based on Signal Transition
    Graphs (STGs).
  • Case study on lysis-lysogeny switch in Lambda
    phage.
  • Conclusions and future work.

3
Modelling Genetic Networks
  • Genetic regulatory networks (GRNs) are complex
    control structures mediating cell function.
  • Require practical modelling and analysis
    techniques.
  • Kinetic parameters lacking for construction of
    meaningful quantitative models.
  • Qualitative approaches often used for gaining
    initial insights.

Kobiler et. al. 2005
4
Boolean Networks
  • Qualitative model Boolean networks (BNs).
  • Regulatory entities abstracted to binary
    switches.
  • Behaviour of each switch given by Boolean
    function over inputs.
  • Synchronous or asynchronous interpretation.
  • BNs ? circuits.

a b c a b c 0 0 0 0
0 1 0 0 1 0 0 1 0 1 0
1 0 1 0 1 1 1 0 1 1 0
0 0 0 0 1 0 1 0 1 0 1
1 0 1 0 0 1 1 1 1 1 0
Circuit equations a b b ac c a
5
Aim
  • Synchronous BN interpretation arguably
    unrealistic.
  • Asynchronous BNs more realistic, but capture too
    rich, non-deterministic behaviour ? unrealisable
    in practice.
  • Require realistic qualitative modelling approach
    with appropriate analysis techniques and tools.
  • Solution
  • Use asynchronous approach.
  • Remove unrealisable behaviour using techniques
    from asynchronous circuit design.
  • Based on speed-independent (SI) circuits
  • functions correctly regardless of gate delays.

6
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

7
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1
Environment
STG
a
b
a
c
C
b
c
a-
b-
c-
8
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1 b 1
Environment
STG
a
b
a
c
C
b
c
a-
b-
c-
9
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1 b 1 c 1
Environment
STG
a
b
a
c
C
b
c
a-
b-
c-
10
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1 b 1 c 1 a 0
Environment
STG
a
b
a
c
C
b
c
a-
b-
c-
11
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1 b 1 c 1 a 0 b 0
Environment
STG
a
b
a
c
C
b
c
a-
b-
c-
12
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1 b 1 c 1 a 0 b 0 c 0
Environment
STG
a
b
a
c
C
b
c
a-
b-
c-
13
Asynchronous Circuit Design
  • Signal transition graphs (STGs) are specification
    language based on Petri nets ? well founded
    techniques/tools.
  • Regulatory entities ? Boolean variables ?
    signals.
  • Input, output and internal signals (output
    internal local).
  • Transitions model signal change, e.g. a from a0
    to a1.

a 1 b 1 c 1 a 0 b 0 c 0
Environment
STG
a
b
a
c
C
b
c
a-
b-
Capture contract between circuit and environment
c-
14
Relationship between BNs and STGs
Circuit equation (BN) c ab c(a b)
a
b
c
Models most general environment!
a-
b-
a-
a
c-
  • BN ? STG straightforward.
  • Equation loses environmental information ?
    STGs more useful for analysis

c-
c
b-
b
15
Speed-Independent (SI) Circuits
  • Function correctly independent of gate delay.
  • SI requires output persistency (OP)
  • no choices involving local transitions.
  • OP violation ? non-determinism.
  • Choices between input transitions models
    non-deterministic decision in the environment
    OK.

16
Speed-Independent (SI) Circuits
  • Function correctly independent of gate delay.
  • SI requires output persistency (OP)
  • no choices involving local transitions.
  • OP violation ? non-determinism.
  • Choices between input transitions models
    non-deterministic decision in the environment
    OK.

Speed-independent (SI) in specified environment
17
Speed-Independent (SI) Circuits
  • Function correctly independent of gate delay.
  • SI requires output persistency (OP)
  • no choices involving local transitions.
  • OP violation ? non-determinism.
  • Choices between input transitions models
    non-deterministic decision in the environment
    OK.

a-
a
b
c
a-
b-
c-
Add extra transition a-
18
Speed-Independent (SI) Circuits
  • Function correctly independent of gate delay.
  • SI requires output persistency (OP)
  • no choices involving local transitions.
  • OP violation ? non-determinism.
  • Choices between input transitions models
    non-deterministic decision in the environment
    OK.

a-
a
b
c
a-
b-
c-
Not SI c disabled by a-
19
Speed-Independent (SI) Circuits
  • Function correctly independent of gate delay.
  • SI requires output persistency (OP)
  • no choices involving local transitions.
  • OP violation ? non-determinism.
  • Choices between input transitions models
    non-deterministic decision in the environment
    OK.
  • Exception choices involving only local
    transitions can be left in model
  • should be documented
  • if represent stochastic phenomenon, can be
    handled in SI manner with arbiters.

a-
a
b
c
a-
b-
c-
20
Approach Overview
Identify OP violations (auto)
PN analysis tools
(auto)
BN
STG
SI Circuit
STG analysis tools
User assumptions (priorities)
21
Refinement Approach
c ab c(a b)
22
Refinement Approach
Identify all OP violations c disabled by a-
c disabled by b- c- disabled by a c-
disabled by b
23
Refinement Approach
Identify all OP violations c disabled by a-
c disabled by b- c- disabled by a c-
disabled by b
  • User adds priorities
  • slow environment
  • relative reaction rates

24
Refinement Approach
Identify all OP violations c disabled by a-
c disabled by b- c- disabled by a c-
disabled by b
  • User adds priorities
  • slow environment
  • relative reaction rates

25
Refinement Approach
Identify all OP violations c disabled by a-
c disabled by b- c- disabled by a c-
disabled by b
  • User adds priorities
  • slow environment
  • relative reaction rates

E.g.assume c faster than a-
26
Refinement Approach
Identify all OP violations c disabled by a-
c disabled by b- c- disabled by a c-
disabled by b
  • User adds priorities
  • slow environment
  • relative reaction rates

E.g.assume c faster than a-
Prioritise c over a- when both enabled by
capturing when a- can fire but c cannot.
27
Refinement Approach
Identify all OP violations c disabled by a-
c disabled by b- c- disabled by a c-
disabled by b
  • User adds priorities
  • slow environment
  • relative reaction rates

E.g.assume c faster than a-
Prioritise c over a- when both enabled by
capturing when a- can fire but c cannot.
28
All OP Violations Resolved
Priorities assumed c faster than a-, c
faster than b- c- faster than a, c- faster
than b
Refine OP violations (automated)
29
Resynthesized STG
  • Optimised using circuit synthesis tool Petrify.
  • STG is SI and, surprisingly, contains more
    behaviour than original, i.e. can cope with more
    demanding environment than one intended.

30
Case Study Lysis-Lysogeny Switch in Lambda Phage
Circuit
Inputs CI (repressor) Internal CII (trans.
activator), Int (integrase), Xis
(excisionase) Outputs Intg (integrated)
Ptashne, 2004
Thomas et. al.,1990
31
OP Violations in Lambda Phage
32
OP Violations in Lambda Phage
OP violations Xis disabled by CI Xis-
disabled by CI- Int disabled by CI Int-
disabled by CI - CII disabled by CI CII -
disabled by CI- Intg- disabled by Int- Intg-
disabled by Xis- Intg disabled by Int- Int/1
disabled by CII-
33
OP Violations in Lambda Phage
OP violations Xis disabled by CI Xis-
disabled by CI- Int disabled by CI Int-
disabled by CI - CII disabled by CI CII -
disabled by CI- Intg- disabled by Int- Intg-
disabled by Xis- Intg disabled by Int- Int/1
disabled by CII-
Environment
34
OP Violations in Lambda Phage
OP violations Xis disabled by CI Xis-
disabled by CI- Int disabled by CI Int-
disabled by CI - CII disabled by CI CII -
disabled by CI- Intg- disabled by Int- Intg-
disabled by Xis- Intg disabled by Int- Int/1
disabled by CII-
Environment
Resolve by assuming slow environment
35
OP Violations in Lambda Phage
35
OP violations Xis disabled by CI Xis-
disabled by CI- Int disabled by CI Int-
disabled by CI - CII disabled by CI CII -
disabled by CI- Intg- disabled by Int- Intg-
disabled by Xis- Intg disabled by Int- Int/1
disabled by CII-
Environment
Resolve by assuming slow environment
36
Final SI STG
  • Much less cluttered.
  • Remaining OP violations
  • Intg- disabled by Int-
  • Intg- disabled by Xis-
  • Intg disabled by Int-
  • Heart of lysis-lysogeny
  • switch (stochastic)
  • Can now be analysed
  • further with PN and STG tools.

37
Conclusions
  • BN ? STG ? SI STG.
  • Framework for obtaining realistic models of GRNs
    using notion of SI circuits
  • refine unrealisable behaviour based on user
    knowledge
  • identifying and documenting missing information.
  • STG construction and refinement automated.
  • Re-use existing PN and STG tools/techniques for
    analysis.
  • Not all OP violations may always be resolved ?
    document.
  • Future work
  • further case studies
  • generalise approach to multi-valued networks
  • investigate application to synthetic biology.

38
Thanks
38
  • A Case for Using Signal Transition Graphs for
    Analysing and Refining Genetic Network
  • Richard Banks, Victor Khomenko and Jason Steggles
  • http//bioinf.ncl.ac.uk/gnapn/
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