Targeting Tiled Architectures in Design Exploration

1
Targeting Tiled Architectures in Design
Exploration

• Lilian Bossuet1, Wayne Burleson2, Guy Gogniat1,
• Vikas Anand2, Andrew Laffely2, Jean-Luc Philippe1

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Outline

• Introduction Design Space Exploration
• Design Space of Reconfigurable Architecture
• A Target Architecture aSoC
• Proposition of Design Space Exploration Flow
• Results
• Conclusion and Future Work

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Design Space Exploration Motivations

• Design solutions for new telecommunication and
  multimedia applications targeting embedded
  systems
• Optimization and reduction of SoC power
  consumption
• Increase computing performance
• Increase parallelism
• Increase speed
• Be flexible
• Take into account run-time reconfiguration
• Targeting multi-granularity (heterogeneous)
  architectures

4
Design Space Exploration Flow

• Progressive design space reduction
• iterative exploration
• refinement of architecture model
• increase of performance estimation accuracy
• One level of abstraction for one level of
  estimation accuracy

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Outline

• Introduction Design Exploration Flow Principe
• Design Space of Reconfigurable Architecture
• A Target Architecture aSoC
• Proposition of Design Space Exploration Flow
• Results
• Conclusion and Future Works

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Reconfigurable Architectures

• Bridging the flexibility gap between ASICs and
  microprocessor Hartenstein DATE 2001
• Energy efficient and solution to low power
  programmable DSP Rabaey ICASSP 1997, FPL 2000
• Run Time Reconfigurable Compton Hauck
  1999
• A key ingredient for future silicon
  platforms Schaumont all. DAC 2001

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Design Space of Reconfigurable Architecture
RECONFIGURABLE ARCHITECTURES (R-SOC)
MULTI GRANULARITY (Heterogeneous)
FINE GRAIN (FPGA)
COARSE GRAIN (Systolic)
Processor Coprocessor
Tile-Based Architecture
Coarse Grain Coprocessor
Fine Grain Coprocessor
Island Topology
Hierarchical Topology
Linear Topology
Hierarchical Topology
Mesh Topology

• RAW
• CHESS
• MATRIX
• KressArray
• Systolix Pulsedsp

• Chameleon
• REMARC
• Morphosys

• Pleiades
• Garp
• FIPSOC
• Triscend E5
• Triscend A7
• Xilinx Virtex-II Pro
• Altera Excalibur
• Atmel FPSIC

• Xilinx Virtex
• Xilinx Spartran
• Atmel AT40K
• Lattice ispXPGA

• Altera Stratix
• Altera Apex
• Altera Cyclone

• Systolic Ring
• RaPiD
• PipeRench

• DART
• FPFA

• aSoC
• E-FPFA

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Outline

• Introduction Design Exploration Flow Principe
• Design Space of Reconfigurable Architecture
• A Target Architecture aSoC
• Proposition of Design Space Exploration Flow
• Results
• Conclusion and Future Works

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A Target Architecture aSoC

• Adaptive System-on-a-Chip (aSoC)
• Tiled architecture containing many heterogeneous
  processing cores (RISC, DSP, FPGA, Motion
  Estimation, Viterbi Decoder)
• Mesh communication network controlled with
  statically determined communication schedule
• A scalable architecture.

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aSoC Architecture
tile
uProc

• Heterogeneous Cores

MUL
FPGA
MUL
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aSoC Communications Interface

• Interface Crossbar
• inter-tile transfer
• tile to core transfer
• Interconnect/Instruction Memory
• contains instructions to configure the interface
  crossbar (cycle-by-cycle)
• Interface Controller
• selects the instruction
• Coreports
• data interface and storage for transfers with the
  tile IP core
• Dynamic Voltage and Frequency Selection
• Dynamic Power Management

Core
Coreports
Interface Crossbar
North
North
South
South
East
East
West
West
Outputs
Inputs
Local
Config
.
Local
Decoder
Controller
Frequency
Voltage
North to South East
PC
Instruction Memory
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aSoC Exploration ...

• Type of tiles
• Number of each type of tile
• Placement of the tiles
• Intern architecture of reconfigurable tiles (FPGA
  core)
• Communication scheduling

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Outline

• Introduction Design Exploration Flow Principe
• Design Space of Reconfigurable Architecture
• A Target Architecture aSoC
• Proposition of Design Space Exploration Flow
• Results
• Conclusion and Future Work

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Design Space Exploration Goals

• Goal Rapid exploration of various architectural
  solutions to be implemented on heterogeneous
  reconfigurable architectures (aSoC) in order to
  select the most efficient architecture for one or
  several applications
• Take place before architectural synthesis
  (algorithmic specification with high level
  abstraction language)
• Estimations are based on a functional
  architecture model (generic, technology-independen
  t)
• Iterative exploration flow to progressively
  refine the architecture definition, from a coarse
  model to a dedicated model

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Design Exploration Flow Targeting Tiled
Architecture
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Application Analysis

• Use of algorithmic metrics and dedicated
  scheduling algorithms to highlight the target
  architectures
• Algorithmic metrics
• Characterize the application orientation
• Processing
• Memory
• Control
• Characterize the application potential
  parallelism
• Processing
• Memory

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Tile Exploration with 3 steps

• Projection
• Link between necessary resources (application)
  and available resources (tile)
• Use of an allocation algorithm based on
  communication costs reduction
• Composition
• Take into account of the function scheduling to
  estimate additional resources (register, mux, )
  
• Estimation
• performance interval computation (lower and upper
  bounds)
• speed/resource utilization/power characterization

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aSoC Builder

• Environment AppMapper
• Partition and assignment
• based on Run Time Estimation
• Compilation
• Communication Scheduling
• Core compilation
• Generate tiles configuration
• Communications instructions
• Bitstreams (for reconfigurable tile)
• RISC instructions

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aSoC Analysis

• Use the results of previous steps
• Functions scheduling
• Tile allocation
• Communication scheduling
• Complete estimation of the proposed solution
• Global execution time
• Global power consumption
• Total area

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Outline

• Introduction Design Exploration Flow Principe
• Design Space of Reconfigurable Architecture
• A Target Architecture aSoC
• Proposition of Design Space Exploration Flow
• Results
• Conclusion and Future Work

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Results

• aSoC architecture (UMASS)
• Prototype of aSoC interconnect
• Technology 0.18 µm
• Clock speed of 400 MHz
• AppMapper (UMASS)
• Several mapped applications
• Matrix operations
• Median Filter
• Viterbi decoder
• DCT

• Tile exploration (UBS)
• Application analysis
• Intelligent Camera (motion detection)
• Matching Pursuit
• Projection step
• Lee DCT
• Matrix operations

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Outline

• Introduction Design Exploration Flow Principe
• Design Space of Reconfigurable Architecture
• A Target Architecture aSoC
• Proposition of Design Space Exploration Flow
• Results
• Conclusion and Future Work

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Conclusion and future work

• Conclusion
• Original design exploration flow working at a
  high level of abstraction
• Fast and flexible (use of functional view of the
  architectures)
• Targeting an efficient reconfigurable
  architecture aSoC
• Statically-scheduled, point-to-point
  communications
• Future Work
• Development of larger set of design exploration
  benchmarks
• Exploration of other configurable systems

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Thank you ...
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Previous Work

• Xplorer - University of Kaiserslautern, Germany
  Hartenstein PATMOS 2000
• Targets a mesh coarse grain architecture The
  KressArray a fast reconfigurable ALUs
• Gives design guidance concerning the size of the
  array, the available operators, the
  communication architecture and the connection
  structure.
• Controlled by performance and power estimations.
• Starts with high level specification of
  application (ALE-X language).
• RAW - Massachusetts Institute of Technology, USA
  Moritz FCCM 1998
• Targets a reminiscent coarse grained FPGA The
  MIT Raw Microprocessor
• Answers to the balance problem to determine the
  best division of VLSI resources among computing,
  memory and communication.
• Answers to the grain problem to determine the
  optimum size of each architecture tiles
• Use several models architecture model, costs
  model and performance model

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HCDFG Hierarchical Control Data Flow Graph
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Applications Metrics
Y. Le Moullec, N. Ben Amor, J-Ph. Diguet, M. Abid
and J-L. Philippe. Multi-Granularity Metrics for
the Era of Strongly Personalized SOCs.In DATE
2002, Munich, Germany, March 2002