Multilevel FullChip Routing for the XBased Architecture

1
Multilevel Full-Chip Routing for the X-Based
Architecture

• Tsung-Yi Ho, Chen-Feng Chang, Yao-Wen Chang, and
  Sao-Jie Chen
• Graduate Institute of Electronics Engineering
• Department of Electrical Engineering
• National Taiwan University
• Taipei, Taiwan

2
Agenda
Introduction
3
Wiring Dominates Nanometer Design

• As integrated circuit geometries keep shrinking,
  interconnect delay has become the dominant factor
  in determining circuit performance.

For 90 nm technology, interconnect delay will
account for 75 of the overall delay.
Source Cadence Design System
4
Solutions

• Timing optimization techniques
• Wire sizing
• Buffer insertion
• Gate sizing

• New IC technologies
• Copper and low-k dielectrics
• X-architecture

5
Manhattan- vs. X-Architecture
Source Cadence
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X-Architecture

• X-initiative
• At least 42 members.
• Veritable supply chain from IP and design
  implementation to photomask and manufacturing.

TC90400XBG (Digital TV) by Toshiba

• Impacts on EDA tools
• Placement and Routing
• Extraction

7
Routing Trends

• Billions of transistors may be fabricated in a
  single chip for nanometer technology.
• Need tools for very large-scale designs.
• Framework evolution for CAD tools

Flat
Hierarchical
Multilevel
Source Intel at ISSCC-03
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Two-Stage Routing

• Global routing
• Partition the routing area into tiles.
• Find tile-to-tile paths for all nets.
• Attempt to optimize given objectives.
• Detailed routing
• Assign actual tracks and vias for nets.

9
Flat Routing Framework

• Flat Framework
• Sequential approaches
• Maze searching
• Line searching
• Concurrent approaches
• Network-flow based algorithms
• Linear assignment formulation
• Drawback hard to handle larger problems

10
Hierarchical Routing Framework

• Hierarchical Framework
• Top-down divide and conquer
• Drawback lack the global information for the
  interaction
• among subregions

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Multilevel Framework

• It has been successfully applied to partitioning,
  floorplanning, placement and routing in VLSI
  physical design and many more.
• Ingredients
• Bottom-up Coarsening Iteratively groups a set of
  circuit components and collects global
  information.
• Top-down Uncoarsening Iteratively ungroups
  clustered components and refines the solution.

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Previous Multilevel Routing Frameworks

• Multilevel full-chip routing frameworks have
  attracted much attention recently.
• Cong et al., Multilevel approach to full-chip
  gridless routing, ICCAD 2001.
• Lin and Chang, A novel framework for multilevel
  routing considering routability and performance,
  ICCAD 2002.
• Ho et al., A fast crosstalk- and
  performance-driven multilevel routing system,
  ICCAD 2003.
• Ho et al., Multilevel Routing with Antenna
  Avoidance,ISPD 2004.

Manhattan-based multilevel routers
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Our X-Multilevel Routing Framework
The 1st X-Based Multilevel Full-Chip Router
Perform trapezoid-shaped track assignment for
long segments on trapezoid panels, and short
segments are routed by a point-to-path maze
router.
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Benefits of Track Assignment

• Good for run-time reduction
• Effective for wirelength minimization

Perform track assignment for longer and diagonal
segments
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Agenda
Introduction
X-Architecture Steiner Tree
Multilevel X Routing Framework
Routability-Driven Pattern Routing
Trapezoid-Shaped Track Assignment
Experimental Results
Conclusions
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Research on Octilinear Steiner Trees

• Related work
• C. S. Coulston, Constructing exact octagonal
  Steiner minimal trees, GLSVLSI 2003.
• A. B. Kahng et al., High scalable algorithms for
  rectilinear and octilinear Steiner trees, ASPDAC
  2003.
• Q. Zhu et al., Efficient octilinear Steiner tree
  construction based on spanning graphs, ASPDAC
  2004.
• For the previous approaches, those with
  relatively better quality may not achieve good
  efficiency.

Our work
X-Steiner Tree Algorithm Based on Delaunay
Triangulation
Optimal Routing for 3-Terminal Nets on the
X-Architecture
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Optimal 2-Terminal Net Routing Based on
X-Architecture

• 2-terminal Net Routing

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Optimal 3-Terminal Net Routing Based on
X-Architecture

• 3-terminal Net Routing

1
1
1
?
2
2
2
Merged Region
Bounding box of 900 and 1800 segments
Bounding box of 450 and 1350 segments

• Lemma
• The optimal routing solution of a 3-terminal net,
  of which one
• terminal is located in the merged region of the
  other two
• terminals, is the Octilinear Minimum Spanning
  Tree (OMST) of it.

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Optimal 3-Terminal Net Routing Case I
R1
R2
R3
R4
1
a
b
2
R4
R3
R1
R2
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Optimal 3-Terminal Net Routing Case II
R1
R2
R3
R4
1
a
b
2
R4
R3
R1
R2
The optimal 3-terminal net routing is the OMST of
these three points and Steiner point a (b).
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Optimal 3-Terminal Net Routing Case III
R1
R2
R3
R4
1
2
R4
R3
R1
R2
The optimal 3-terminal net routing is the OMST of
these three points and Steiner point S.
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3-Terminal Net Routing on X-Architecture (X3TR)

• Theorem
• The X3TR algorithm finds the optimal routing
  of the minimum wirelength for a 3-terminal net on
  the X-architecture in constant time.

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X-Steiner Tree Algorithm Based on Delaunay
Triangulation
7.6
13.8
8.4
12.6
7.0
9.6
9.8
12.6
7.4
8.6
11.8
8.6
10.6
13.4
(b)
(a)
(c)
Run X3TR for triangles in increasing order
Compute optimal wirelength of OMST for each
triangle and sort them
Delaunay triangulation
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Local Refinement for Wirelength
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X-Steiner Tree Algorithm Based on Delaunay
Triangulation
7.6
13.8
8.4
12.6
7.0
9.6
9.8
12.6
7.4
8.6
11.8
8.6
10.6
13.4
(b)
(a)
(c)
Compute optimal wirelength of OMST for each
triangle and sort them
Delaunay triangulation

• O(n lg n)

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Agenda
Introduction
X-Architecture Steiner Tree
Multilevel X Routing Framework
Routability-Driven Pattern Routing
Trapezoid-Shaped Track Assignment
Experimental Results
Conclusions
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Multilevel X Routing Model
tile
Multilevel Routing Graph
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Global Pattern Routing 1-Bend

• 1-Bend Pattern routing

m
m
n
n
(a)
(b)
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Global Pattern Routing 2-Bend

• 2-Bend Pattern routing

m
m
n
n
(c)
(d)
Shortest path length
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Cost Function in Global Pattern Routing

• Gi (Vi , Ei) multilevel routing graph at
  level i.
• Define
• Then
• where Ce is the congestion of edge e
• and
• where pe and de are the capacity and density
  associated with e, respectively.

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Agenda
Introduction
X-Architecture Steiner Tree
Multilevel X Routing Framework
Routability-Driven Pattern Routing
Trapezoid-Shaped Track Assignment
Experimental Results
Conclusions
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Trapezoid-Shaped Track Assignment

• Trapezoid-Shaped Track Assignment Problem
• Input
• a set of segments S
• a set of tracks T in a trapezoid panel
• a cost function F S x T ? N, which represents
  the cost of assigning a segment to a track
• Objective
• find an assignment that minimizes the sum of the
  costs.

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Wire Pitch for X-Routing
How to connect HV and diagonal tracks?
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Connect to the Grid Point
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Trapezoid Shape Track Assignment
Obstacles
Left Segments
1
2
Middle Segments
3
4
Right Segments
Trapezoid Panel
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Our X-Multilevel Routing Framework Recap
Perform trapezoid-shaped track assignment for
long segments on trapezoid panels, and short
segments are routed by a point-to-path maze
router.
37
Agenda
Introduction
X-Architecture Steiner Tree
Multilevel X Routing Framework
Routability-Driven Pattern Routing
Trapezoid-Shaped Track Assignment
Experimental Results
Conclusions
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Experimental Setting

• Language C
• Library STL, LEDA, LayoutDB (UCLA)
• Platform 1GHz Sun Blade 2000 with 1GB memory
• Benchmarks

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Experimental Results
Compared with the Manhattan-based multilevel
router, our X-router reduced
wirelength by 18.7
, average delay by 8.8
, and run-time by 13.
Davg Average delay (Elmore delay model)
ICCAD 2003 T.-Y. Ho, Y.-W. Chang, S.-J. Chen,
and D. T. Lee, A fast crosstalk- and
performance-driven multilevel routing system.
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X Routing Results of S38417
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Agenda
Introduction
X-Architecture Steiner Tree
Multilevel X Routing Framework
Routability-Driven Pattern Routing
Trapezoid-Shaped Track Assignment
Experimental Results
Conclusions
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Conclusions

• We propose the first X-based multilevel full-chip
  router.
• Optimal routing for 3-terminal nets on the
  X-architecture in constant time
• General X-Steiner tree algorithm based
  ondelaunay triangulation
• Virtual tracks for effective diagonal
  routingresource usage
• The experimental results have shown that
  ourapproach reduced wirelength by 18.7 and
  average delay by 8.8 with similar routing
  completion ratesand via counts.
• Our future work lies in an integrated multilevel
  placement and routing system for the
  X-architecture.

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Acknowledgements

• Thank Dr. Cliff Hou, Dr. LC Lu, and Mr. Ken Wang
  of TSMC for their helpful discussions.
• This work was partially supported by grants from
  UMC and NSC, Taiwan.

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Thank You!!